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| author | Eddie Hung <eddieh@ece.ubc.ca> | 2019-04-04 07:54:42 -0700 |
|---|---|---|
| committer | Eddie Hung <eddieh@ece.ubc.ca> | 2019-04-04 07:54:42 -0700 |
| commit | 572603409c3f5524f8d4d9e43a168bcfccd94465 (patch) | |
| tree | 042e21e109701a41623170c04ee3c1467a681fc9 /passes | |
| parent | 77755b5a662a11a3dcc18c070e6ea859104fc872 (diff) | |
| parent | d9cb787391143a1749954f9e442fd37a13668b08 (diff) | |
| download | yosys-572603409c3f5524f8d4d9e43a168bcfccd94465.tar.gz yosys-572603409c3f5524f8d4d9e43a168bcfccd94465.tar.bz2 yosys-572603409c3f5524f8d4d9e43a168bcfccd94465.zip | |
Merge branch 'map_cells_before_map_luts' into xc7srl
Diffstat (limited to 'passes')
| -rw-r--r-- | passes/proc/proc_mux.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/proc/proc_mux.cc b/passes/proc/proc_mux.cc index 7d3d23408..bac2dc2cd 100644 --- a/passes/proc/proc_mux.cc +++ b/passes/proc/proc_mux.cc @@ -361,7 +361,7 @@ RTLIL::SigSpec signal_to_mux_tree(RTLIL::Module *mod, SnippetSwCache &swcache, d } // Transform into a $shiftx where possible - if (shiftx && last_mux_cell->type == "$pmux") { + if (shiftx && last_mux_cell && last_mux_cell->type == "$pmux") { // Create bit-blasted $shiftx-es that shifts by the address line used in the case statement auto pmux_b_port = last_mux_cell->getPort("\\B"); auto pmux_y_port = last_mux_cell->getPort("\\Y"); |