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| author | Eddie Hung <eddie@fpgeh.com> | 2019-06-24 22:12:55 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-24 22:12:55 -0700 |
| commit | 5605002d8a583409a56d1187460de1f4a03d8454 (patch) | |
| tree | 2e8af6b77010090248bae99fabdbebdf209fbe3b /passes | |
| parent | 4fadb471a3028487d4b05b3e343b3be49349f78b (diff) | |
| download | yosys-5605002d8a583409a56d1187460de1f4a03d8454.tar.gz yosys-5605002d8a583409a56d1187460de1f4a03d8454.tar.bz2 yosys-5605002d8a583409a56d1187460de1f4a03d8454.zip | |
More meaningful error message
Diffstat (limited to 'passes')
| -rw-r--r-- | passes/techmap/abc9.cc | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc index c8272153d..6356d4fbf 100644 --- a/passes/techmap/abc9.cc +++ b/passes/techmap/abc9.cc @@ -118,6 +118,8 @@ void handle_loops(RTLIL::Design *design) auto jt = box_module->attributes.find("\\abc_scc_break"); if (jt != box_module->attributes.end()) { auto it = cell->connections_.find(RTLIL::escape_id(jt->second.decode_string())); + if (it == cell->connections_.end()) + log_error("abc_scc_break attribute value '%s' does not exist as port on module '%s'\n", jt->second.decode_string().c_str(), log_id(box_module)); log_assert(it != cell->connections_.end()); auto &c = *it; SigBit b = cell->getPort(RTLIL::escape_id(jt->second.decode_string())); |