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| author | Eddie Hung <eddieh@ece.ubc.ca> | 2019-03-19 17:44:33 -0700 |
|---|---|---|
| committer | Eddie Hung <eddieh@ece.ubc.ca> | 2019-03-19 17:44:33 -0700 |
| commit | 5445cd4d00349f9d04f9e78c7c2804306fac6b65 (patch) | |
| tree | e95ed2958855afbf5ad375028cea5cfd54ec1006 /passes | |
| parent | ae2a625d0507c9e7476497e0064ffa003aa761f1 (diff) | |
| download | yosys-5445cd4d00349f9d04f9e78c7c2804306fac6b65.tar.gz yosys-5445cd4d00349f9d04f9e78c7c2804306fac6b65.tar.bz2 yosys-5445cd4d00349f9d04f9e78c7c2804306fac6b65.zip | |
Add support for variable length Xilinx SRL > 128
Diffstat (limited to 'passes')
| -rw-r--r-- | passes/techmap/shregmap.cc | 6 |
1 files changed, 0 insertions, 6 deletions
diff --git a/passes/techmap/shregmap.cc b/passes/techmap/shregmap.cc index bd537e7c2..a060b55df 100644 --- a/passes/techmap/shregmap.cc +++ b/passes/techmap/shregmap.cc @@ -165,12 +165,6 @@ struct ShregmapTechXilinx7 : ShregmapTech } log_assert(shiftx); - // Cannot implement variable-length shift registers - // greater than 128 since Q31 cannot be output onto - // fabric - if (GetSize(taps) > 128) - return false; - // Only map if $shiftx exclusively covers the shift register if (GetSize(taps) != shiftx->getParam("\\A_WIDTH").as_int()) return false; |