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author | Claire Wolf <clifford@clifford.at> | 2020-01-28 17:40:28 +0100 |
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committer | GitHub <noreply@github.com> | 2020-01-28 17:40:28 +0100 |
commit | 4ddaa70fd6363096bf0cb1bc5e7cb8fa8ed21ad2 (patch) | |
tree | 1ee2ffb6abec353f6a04a878c4ef60449576669e /passes | |
parent | 086c133ea58179b1b1a14bff972355c68f926e8d (diff) | |
parent | 4a805108776f563bcd7550d1331a73a50512fbe2 (diff) | |
download | yosys-4ddaa70fd6363096bf0cb1bc5e7cb8fa8ed21ad2.tar.gz yosys-4ddaa70fd6363096bf0cb1bc5e7cb8fa8ed21ad2.tar.bz2 yosys-4ddaa70fd6363096bf0cb1bc5e7cb8fa8ed21ad2.zip |
Merge pull request #1567 from YosysHQ/eddie/sat_init_warning
sat: suppress 'Warning: ignoring initial value on non-register: ...' when init[i] = 1'bx
Diffstat (limited to 'passes')
-rw-r--r-- | passes/sat/sat.cc | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/passes/sat/sat.cc b/passes/sat/sat.cc index 430bba1e8..436ac1b01 100644 --- a/passes/sat/sat.cc +++ b/passes/sat/sat.cc @@ -269,7 +269,8 @@ struct SatHelper for (int i = 0; i < lhs.size(); i++) { RTLIL::SigSpec bit = lhs.extract(i, 1); if (rhs[i] == State::Sx || !satgen.initial_state.check_all(bit)) { - removed_bits.append(bit); + if (rhs[i] != State::Sx) + removed_bits.append(bit); lhs.remove(i, 1); rhs.remove(i, 1); i--; |