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| author | Eddie Hung <eddie@fpgeh.com> | 2020-03-30 08:22:12 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-03-30 08:22:46 -0700 |
| commit | 4d897975a8fe76191c39442eb7603723a2b84e1d (patch) | |
| tree | 5aa754db5cdccf7458720d08c9bd582008b61556 /passes | |
| parent | f64d59d824424756794fcb8c1fad4d6a088358d8 (diff) | |
| download | yosys-4d897975a8fe76191c39442eb7603723a2b84e1d.tar.gz yosys-4d897975a8fe76191c39442eb7603723a2b84e1d.tar.bz2 yosys-4d897975a8fe76191c39442eb7603723a2b84e1d.zip | |
Code review fixes
Diffstat (limited to 'passes')
| -rw-r--r-- | passes/memory/memory_share.cc | 4 | ||||
| -rw-r--r-- | passes/opt/opt_expr.cc | 2 |
2 files changed, 3 insertions, 3 deletions
diff --git a/passes/memory/memory_share.cc b/passes/memory/memory_share.cc index 0111c2309..8b9d9a04d 100644 --- a/passes/memory/memory_share.cc +++ b/passes/memory/memory_share.cc @@ -670,13 +670,13 @@ struct MemoryShareWorker void operator()(RTLIL::Module* module) { + std::map<std::string, std::pair<std::vector<RTLIL::Cell*>, std::vector<RTLIL::Cell*>>> memindex; + this->module = module; sigmap.set(module); sig_to_mux.clear(); conditions_logic_cache.clear(); - std::map<std::string, std::pair<std::vector<RTLIL::Cell*>, std::vector<RTLIL::Cell*>>> memindex; - sigmap_xmux = sigmap; for (auto cell : module->cells()) { diff --git a/passes/opt/opt_expr.cc b/passes/opt/opt_expr.cc index c13184025..68d6ea82b 100644 --- a/passes/opt/opt_expr.cc +++ b/passes/opt/opt_expr.cc @@ -31,7 +31,7 @@ PRIVATE_NAMESPACE_BEGIN bool did_something; -void replace_undriven(RTLIL::Module *module, const CellTypes& ct) +void replace_undriven(RTLIL::Module *module, const CellTypes &ct) { SigMap sigmap(module); SigPool driven_signals; |