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| author | Eddie Hung <eddieh@ece.ubc.ca> | 2019-03-19 15:05:08 -0700 |
|---|---|---|
| committer | Eddie Hung <eddieh@ece.ubc.ca> | 2019-03-19 15:05:08 -0700 |
| commit | 4cd8f0297381c5fb9fe3b8cbb22d4240f2aaae63 (patch) | |
| tree | 17daef0a82a7f9bd6ff9bfde841ba3cf2dadec4c /passes | |
| parent | f239cb821edb86c3ec48782139e982819f073a7c (diff) | |
| download | yosys-4cd8f0297381c5fb9fe3b8cbb22d4240f2aaae63.tar.gz yosys-4cd8f0297381c5fb9fe3b8cbb22d4240f2aaae63.tar.bz2 yosys-4cd8f0297381c5fb9fe3b8cbb22d4240f2aaae63.zip | |
shregmap -tech xilinx to delete $shiftx for var length SRL
Diffstat (limited to 'passes')
| -rw-r--r-- | passes/techmap/shregmap.cc | 13 |
1 files changed, 3 insertions, 10 deletions
diff --git a/passes/techmap/shregmap.cc b/passes/techmap/shregmap.cc index 3b3170e04..bd537e7c2 100644 --- a/passes/techmap/shregmap.cc +++ b/passes/techmap/shregmap.cc @@ -187,19 +187,12 @@ struct ShregmapTechXilinx7 : ShregmapTech if (it == sigbit_to_shiftx_offset.end()) return true; - auto cell_q = cell->getPort("\\Q"); - log_assert(cell_q.is_bit()); - Cell* shiftx = it->second.first; - // FIXME: Hack to ensure that $shiftx gets optimised away - // Without this, Yosys will refuse to optimise away a $shiftx - // where \\A 's width is not perfectly \\B_WIDTH ** 2 - // See YosysHQ/yosys#878 - auto shiftx_bwidth = shiftx->getParam("\\B_WIDTH").as_int(); - shiftx->setPort("\\A", cell_q.repeat(1 << shiftx_bwidth)); - shiftx->setParam("\\A_WIDTH", 1 << shiftx_bwidth); cell->setPort("\\L", shiftx->getPort("\\B")); + cell->setPort("\\Q", shiftx->getPort("\\Y")); + + cell->module->remove(shiftx); return true; } |