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authorEddie Hung <eddie@fpgeh.com>2019-06-17 13:20:29 -0700
committerEddie Hung <eddie@fpgeh.com>2019-06-17 13:20:29 -0700
commit4b9eefe3b6fce79fc0b31a97efde3b5f1ba49cea (patch)
tree7219ae7559bacd801d5d262cab7401245df97103 /passes
parent0c9cf892390941d52a3e35b29d509f4ee19ebae1 (diff)
parent63fc879a5f698803d563a57275cc99a3df2d1414 (diff)
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Merge remote-tracking branch 'origin/xaig' into xc7mux
Diffstat (limited to 'passes')
-rw-r--r--passes/techmap/abc9.cc7
1 files changed, 4 insertions, 3 deletions
diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc
index 9c4e6bb39..184fbfaee 100644
--- a/passes/techmap/abc9.cc
+++ b/passes/techmap/abc9.cc
@@ -599,11 +599,12 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
if (markgroups) cell->attributes["\\abcgroup"] = map_autoidx;
RTLIL::Cell *existing_cell = module->cell(c->name);
if (existing_cell) {
- cell->parameters = std::move(existing_cell->parameters);
- cell->attributes = std::move(existing_cell->attributes);
+ cell->parameters = existing_cell->parameters;
+ cell->attributes = existing_cell->attributes;
}
else {
- cell->parameters = std::move(c->parameters);
+ cell->parameters = c->parameters;
+ cell->attributes = c->attributes;
}
for (auto &conn : c->connections()) {
RTLIL::SigSpec newsig;