abc9: add flop boxes to basic $_DFF_P_ and $_DFF_N_ too

2 files changed, 26 insertions, 19 deletions

diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc
index fbb8356a5..911254aa6 100644
--- a/passes/techmap/abc9.cc
+++ b/passes/techmap/abc9.cc
@@ -314,23 +314,24 @@ struct Abc9Pass : public ScriptPass
 						}
 					}
 					run("design -stash $abc9_map");
-					run("design -load $abc9");
-					run("design -delete $abc9");
-					run("select -unset $abc9_flops");
-					run("techmap -wb -map %$abc9_map"); // techmap user design into submod + $_DFF_[NP]_
+				}
+				run("design -load $abc9");
+				run("design -delete $abc9");
+				run("select -unset $abc9_flops");
+				if (did_something) { // techmap user design into submod + $_DFF_[NP]_
+					run("techmap -wb -max_iter 1 -map %$abc9_map -map +/abc9_map.v");
 					run("design -delete $abc9_map");
 					run("setattr -mod -set whitebox 1 -set abc9_flop 1 -set abc9_box 1 *_$abc9_flop");
 					run("abc9_ops -prep_dff_unmap"); // implement $abc9_unmap design
 				}
-				else {
-					run("design -load $abc9");
-					run("design -delete $abc9");
-					run("select -unset $abc9_flops");
-				}
+				else
+					run("techmap -wb -max_iter 1 -map +/abc9_map.v");
+
 			}
 		}
 
 		if (check_label("pre")) {
+			run("read_verilog -icells -lib -specify +/abc9_model.v");
 			run("scc -set_attr abc9_scc_id {}");
 			if (help_mode)
 				run("abc9_ops -mark_scc -prep_delays -prep_xaiger [-dff]", "(option for -dff)");
diff --git a/passes/techmap/abc9_ops.cc b/passes/techmap/abc9_ops.cc
index 62007c61e..976b6462e 100644
--- a/passes/techmap/abc9_ops.cc
+++ b/passes/techmap/abc9_ops.cc
@@ -128,7 +128,7 @@ void prep_dff_hier(RTLIL::Design *design)
 
 	Design *unmap_design = new Design;
 
-	for (auto module : design->selected_modules())
+	for (auto module : design->modules())
 		for (auto cell : module->cells()) {
 			auto inst_module = design->module(cell->type);
 			if (inst_module && inst_module->attributes.count(ID::abc9_flop)) {
@@ -219,17 +219,23 @@ void prep_dff_map(RTLIL::Design *design)
 
 		D = dff_cell->getPort(ID::D);
 
-		// Add a dummy enable mux feeding DFF.D to ensure that:
-		//   (i) a driving cell exists, so that 'submod' will have
-		//       an output port
-		//   (ii) DFF.Q will exist in this submodule
 		{
-			auto c = module->addCell(NEW_ID, ID($_MUX_));
+			// Add dummy buffers for all module inputs/outputs
+			//   to ensure that these ports exists in the flop box
+			//   created by later submod pass
+			for (auto port_name : module->ports) {
+				auto port = module->wire(port_name);
+				log_assert(GetSize(port) == 1);
+				auto c = module->addBufGate(NEW_ID, port, module->addWire(NEW_ID));
+				// Need to set (* keep *) otherwise opt_clean
+				//   inside submod will blow it away
+				c->set_bool_attribute(ID::keep);
+			}
+			// Add an additional buffer that drives $_DFF_[NP]_.D
+			//   so that the flop box will have an output
 			auto w = module->addWire(NEW_ID);
-			c->setPort(ID::A, D);
-			c->setPort(ID::B, Q);
-			c->setPort(ID::S, State::S0);
-			c->setPort(ID::Y, w);
+			auto c = module->addBufGate(NEW_ID, D, w);
+			c->set_bool_attribute(ID::keep);
 			dff_cell->setPort(ID::D, w);
 			D = w;
 		}