diff options
| author | Eddie Hung <eddie@fpgeh.com> | 2020-06-03 17:35:46 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-06-03 17:35:46 -0700 |
| commit | 45cd323055270ff414419ddf8a9b5d08f40628b5 (patch) | |
| tree | dca3058ce1f8bfa3a030716d40abf662d6733c0f /passes | |
| parent | 46ed0db2ec883a4ce330c81f321511e36e35c0b3 (diff) | |
| parent | 8a11019d382f3eb5a8d95ce64511a1dcbbe2acfe (diff) | |
| download | yosys-45cd323055270ff414419ddf8a9b5d08f40628b5.tar.gz yosys-45cd323055270ff414419ddf8a9b5d08f40628b5.tar.bz2 yosys-45cd323055270ff414419ddf8a9b5d08f40628b5.zip | |
Merge pull request #2082 from YosysHQ/eddie/abc9_scc_fixes
abc9: fixes around handling combinatorial loops
Diffstat (limited to 'passes')
| -rw-r--r-- | passes/techmap/abc9_ops.cc | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/passes/techmap/abc9_ops.cc b/passes/techmap/abc9_ops.cc index 8d55b18a0..16b468b19 100644 --- a/passes/techmap/abc9_ops.cc +++ b/passes/techmap/abc9_ops.cc @@ -719,8 +719,10 @@ void prep_xaiger(RTLIL::Module *module, bool dff) bit_users[bit].insert(cell->name); if (cell->output(conn.first) && !abc9_flop) - for (auto bit : sigmap(conn.second)) - bit_drivers[bit].insert(cell->name); + for (const auto &chunk : conn.second.chunks()) + if (!chunk.wire->get_bool_attribute(ID::abc9_keep)) + for (auto b : sigmap(SigSpec(chunk))) + bit_drivers[b].insert(cell->name); } toposort.node(cell->name); } |