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| author | Eddie Hung <eddie@fpgeh.com> | 2019-09-06 11:38:19 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-09-06 11:38:19 -0700 |
| commit | 39a5d046ea5fe1021520d285723ef0b02dca4d17 (patch) | |
| tree | 334a09db4c98c330d24586431ca9eff6b8129417 /passes | |
| parent | cdc1e1f5c226d3597896555749ecfa3568a66c50 (diff) | |
| download | yosys-39a5d046ea5fe1021520d285723ef0b02dca4d17.tar.gz yosys-39a5d046ea5fe1021520d285723ef0b02dca4d17.tar.bz2 yosys-39a5d046ea5fe1021520d285723ef0b02dca4d17.zip | |
Fix nusers condition in ffP
Diffstat (limited to 'passes')
| -rw-r--r-- | passes/pmgen/xilinx_dsp.pmg | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/passes/pmgen/xilinx_dsp.pmg b/passes/pmgen/xilinx_dsp.pmg index bb3bf90bd..adf30b45a 100644 --- a/passes/pmgen/xilinx_dsp.pmg +++ b/passes/pmgen/xilinx_dsp.pmg @@ -228,6 +228,8 @@ code sigC sigP endcode match ffPmux + if param(dsp, \PREG).as_int() == 0 + if nusers(sigP) == 2 select ffPmux->type.in($mux) choice <IdString> BA {\B, \A} // new-value net must have exactly two users: dsp and ffP @@ -253,13 +255,14 @@ endcode match ffP if param(dsp, \PREG).as_int() == 0 + if nusers(sigP) == 2 select ffP->type.in($dff) // DSP48E1 does not support clock inversion select param(ffP, \CLK_POLARITY).as_bool() - select nusers(port(ffP, \D)) == 2 filter GetSize(port(ffP, \D)) >= GetSize(sigP) slice offset GetSize(port(ffP, \D)) - filter offset+GetSize(sigP) <= GetSize(port(ffP, \D)) && port(ffP, \D).extract(offset, GetSize(sigP)) == sigP + filter offset+GetSize(sigP) <= GetSize(port(ffP, \D)) + filter port(ffP, \D).extract(offset, GetSize(sigP)) == sigP // Check ffPmux (when present) is a $dff enable mux filter !ffPmux || port(ffP, \Q) == port(ffPmux, ffPenpol ? \A : \B) optional |