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| author | Eddie Hung <eddie@fpgeh.com> | 2019-09-18 12:16:03 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-09-18 12:16:03 -0700 |
| commit | 347cbf59bd45345663defa9c99c7fc6563404da6 (patch) | |
| tree | 7f7d33b3a4bec681a20529a77988dd736f8ea4ed /passes | |
| parent | c9fe4d7992078ca0dec2cb7bcc6c58813e73189d (diff) | |
| download | yosys-347cbf59bd45345663defa9c99c7fc6563404da6.tar.gz yosys-347cbf59bd45345663defa9c99c7fc6563404da6.tar.bz2 yosys-347cbf59bd45345663defa9c99c7fc6563404da6.zip | |
Check overflow condition is power of 2 without using int32
Diffstat (limited to 'passes')
| -rw-r--r-- | passes/pmgen/xilinx_dsp.cc | 16 | ||||
| -rw-r--r-- | passes/pmgen/xilinx_dsp.pmg | 4 |
2 files changed, 15 insertions, 5 deletions
diff --git a/passes/pmgen/xilinx_dsp.cc b/passes/pmgen/xilinx_dsp.cc index 786582cfa..8500a6072 100644 --- a/passes/pmgen/xilinx_dsp.cc +++ b/passes/pmgen/xilinx_dsp.cc @@ -337,10 +337,20 @@ void pack_xilinx_dsp(dict<SigBit, Cell*> &bit_to_driver, xilinx_dsp_pm &pm) cell->setParam("\\SEL_MASK", Const("MASK")); if (st.overflow->type == "$ge") { - int B = st.overflow->getPort("\\B").as_int(); - log_assert((B & (B-1)) == 0); // Exact power of 2 + Const B = st.overflow->getPort("\\B").as_const(); + log_assert(std::count(B.bits.begin(), B.bits.end(), State::S1) == 1); + // Since B is an exact power of 2, subtract 1 + // by inverting all bits up until hitting + // that one hi bit + for (auto &b : B.bits) + if (b == State::S0) b = State::S1; + else if (b == State::S1) { + b = State::S0; + break; + } + B.extu(48); - cell->setParam("\\MASK", Const(B-1, 48)); + cell->setParam("\\MASK", B); cell->setParam("\\PATTERN", Const(0, 48)); cell->setPort("\\OVERFLOW", st.overflow->getPort("\\Y")); } diff --git a/passes/pmgen/xilinx_dsp.pmg b/passes/pmgen/xilinx_dsp.pmg index b93162a0e..08cb1f51b 100644 --- a/passes/pmgen/xilinx_dsp.pmg +++ b/passes/pmgen/xilinx_dsp.pmg @@ -361,8 +361,8 @@ match overflow select overflow->type.in($ge) select GetSize(port(overflow, \Y)) <= 48 select port(overflow, \B).is_fully_const() - // Check is exact power of 2 - select (port(overflow, \B).as_int() & (port(overflow, \B).as_int()-1)) == 0 + define <Const> B port(overflow, \B).as_const() + select std::count(B.bits.begin(), B.bits.end(), State::S1) == 1 index <SigSpec> port(overflow, \A) === sigP optional endmatch |