Merge pull request #1818 from YosysHQ/mwk/new-ff-types

Add new FF types to library.

8 files changed, 263 insertions, 66 deletions

diff --git a/passes/cmds/stat.cc b/passes/cmds/stat.cc
index 6f2c2243e..ed51fdc24 100644
--- a/passes/cmds/stat.cc
+++ b/passes/cmds/stat.cc
@@ -117,7 +117,10 @@ struct statdata_t
 				}
 				else if (cell_type.in(ID($mux), ID($pmux)))
 					cell_type = stringf("%s_%d", cell_type.c_str(), GetSize(cell->getPort(ID::Y)));
-				else if (cell_type.in(ID($sr), ID($dff), ID($dffsr), ID($adff), ID($dlatch), ID($dlatchsr)))
+				else if (cell_type.in(
+						ID($sr), ID($ff), ID($dff), ID($dffe), ID($dffsr), ID($dffsre),
+						ID($adff), ID($adffe), ID($sdff), ID($sdffe), ID($sdffce),
+						ID($dlatch), ID($adlatch), ID($dlatchsr)))
 					cell_type = stringf("%s_%d", cell_type.c_str(), GetSize(cell->getPort(ID::Q)));
 			}
 
diff --git a/passes/opt/opt_expr.cc b/passes/opt/opt_expr.cc
index c16f22b38..170afb19c 100644
--- a/passes/opt/opt_expr.cc
+++ b/passes/opt/opt_expr.cc
@@ -467,15 +467,21 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
 
 		if (clkinv)
 		{
-			if (cell->type.in(ID($dff), ID($dffe), ID($dffsr), ID($adff), ID($fsm), ID($memrd), ID($memwr)))
+			if (cell->type.in(ID($dff), ID($dffe), ID($dffsr), ID($dffsre), ID($adff), ID($adffe), ID($sdff), ID($sdffe), ID($sdffce), ID($fsm), ID($memrd), ID($memwr)))
 				handle_polarity_inv(cell, ID::CLK, ID::CLK_POLARITY, assign_map, invert_map);
 
-			if (cell->type.in(ID($sr), ID($dffsr), ID($dlatchsr))) {
+			if (cell->type.in(ID($sr), ID($dffsr), ID($dffsre), ID($dlatchsr))) {
 				handle_polarity_inv(cell, ID::SET, ID::SET_POLARITY, assign_map, invert_map);
 				handle_polarity_inv(cell, ID::CLR, ID::CLR_POLARITY, assign_map, invert_map);
 			}
 
-			if (cell->type.in(ID($dffe), ID($dlatch), ID($dlatchsr)))
+			if (cell->type.in(ID($adff), ID($adffe), ID($adlatch)))
+				handle_polarity_inv(cell, ID::ARST, ID::ARST_POLARITY, assign_map, invert_map);
+
+			if (cell->type.in(ID($sdff), ID($sdffe), ID($sdffce)))
+				handle_polarity_inv(cell, ID::SRST, ID::SRST_POLARITY, assign_map, invert_map);
+
+			if (cell->type.in(ID($dffe), ID($adffe), ID($sdffe), ID($sdffce), ID($dffsre), ID($dlatch), ID($adlatch), ID($dlatchsr)))
 				handle_polarity_inv(cell, ID::EN, ID::EN_POLARITY, assign_map, invert_map);
 
 			handle_clkpol_celltype_swap(cell, "$_SR_N?_", "$_SR_P?_", ID::S, assign_map, invert_map);
@@ -489,12 +495,35 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
 			handle_clkpol_celltype_swap(cell, "$_DFF_N??_", "$_DFF_P??_", ID::C, assign_map, invert_map);
 			handle_clkpol_celltype_swap(cell, "$_DFF_?N?_", "$_DFF_?P?_", ID::R, assign_map, invert_map);
 
+			handle_clkpol_celltype_swap(cell, "$_DFFE_N???_", "$_DFFE_P???_", ID::C, assign_map, invert_map);
+			handle_clkpol_celltype_swap(cell, "$_DFFE_?N??_", "$_DFFE_?P??_", ID::R, assign_map, invert_map);
+			handle_clkpol_celltype_swap(cell, "$_DFFE_???N_", "$_DFFE_???P_", ID::E, assign_map, invert_map);
+
+			handle_clkpol_celltype_swap(cell, "$_SDFF_N??_", "$_SDFF_P??_", ID::C, assign_map, invert_map);
+			handle_clkpol_celltype_swap(cell, "$_SDFF_?N?_", "$_SDFF_?P?_", ID::R, assign_map, invert_map);
+
+			handle_clkpol_celltype_swap(cell, "$_SDFFE_N???_", "$_SDFFE_P???_", ID::C, assign_map, invert_map);
+			handle_clkpol_celltype_swap(cell, "$_SDFFE_?N??_", "$_SDFFE_?P??_", ID::R, assign_map, invert_map);
+			handle_clkpol_celltype_swap(cell, "$_SDFFE_???N_", "$_SDFFE_???P_", ID::E, assign_map, invert_map);
+
+			handle_clkpol_celltype_swap(cell, "$_SDFFCE_N???_", "$_SDFFCE_P???_", ID::C, assign_map, invert_map);
+			handle_clkpol_celltype_swap(cell, "$_SDFFCE_?N??_", "$_SDFFCE_?P??_", ID::R, assign_map, invert_map);
+			handle_clkpol_celltype_swap(cell, "$_SDFFCE_???N_", "$_SDFFCE_???P_", ID::E, assign_map, invert_map);
+
 			handle_clkpol_celltype_swap(cell, "$_DFFSR_N??_", "$_DFFSR_P??_", ID::C, assign_map, invert_map);
 			handle_clkpol_celltype_swap(cell, "$_DFFSR_?N?_", "$_DFFSR_?P?_", ID::S, assign_map, invert_map);
 			handle_clkpol_celltype_swap(cell, "$_DFFSR_??N_", "$_DFFSR_??P_", ID::R, assign_map, invert_map);
 
+			handle_clkpol_celltype_swap(cell, "$_DFFSRE_N???_", "$_DFFSRE_P???_", ID::C, assign_map, invert_map);
+			handle_clkpol_celltype_swap(cell, "$_DFFSRE_?N??_", "$_DFFSRE_?P??_", ID::S, assign_map, invert_map);
+			handle_clkpol_celltype_swap(cell, "$_DFFSRE_??N?_", "$_DFFSRE_??P?_", ID::R, assign_map, invert_map);
+			handle_clkpol_celltype_swap(cell, "$_DFFSRE_???N_", "$_DFFSRE_???P_", ID::E, assign_map, invert_map);
+
 			handle_clkpol_celltype_swap(cell, "$_DLATCH_N_", "$_DLATCH_P_", ID::E, assign_map, invert_map);
 
+			handle_clkpol_celltype_swap(cell, "$_DLATCH_N??_", "$_DLATCH_P??_", ID::E, assign_map, invert_map);
+			handle_clkpol_celltype_swap(cell, "$_DLATCH_?N?_", "$_DLATCH_?P?_", ID::R, assign_map, invert_map);
+
 			handle_clkpol_celltype_swap(cell, "$_DLATCHSR_N??_", "$_DLATCHSR_P??_", ID::E, assign_map, invert_map);
 			handle_clkpol_celltype_swap(cell, "$_DLATCHSR_?N?_", "$_DLATCHSR_?P?_", ID::S, assign_map, invert_map);
 			handle_clkpol_celltype_swap(cell, "$_DLATCHSR_??N_", "$_DLATCHSR_??P_", ID::R, assign_map, invert_map);
diff --git a/passes/opt/pmux2shiftx.cc b/passes/opt/pmux2shiftx.cc
index 9a00f84b9..9f226e12d 100644
--- a/passes/opt/pmux2shiftx.cc
+++ b/passes/opt/pmux2shiftx.cc
@@ -63,11 +63,13 @@ struct OnehotDatabase
 			vector<SigSpec> inputs;
 			SigSpec output;
 
-			if (cell->type.in(ID($adff), ID($dff), ID($dffe), ID($dlatch), ID($ff)))
+			if (cell->type.in(ID($adff), ID($adffe), ID($dff), ID($dffe), ID($sdff), ID($sdffe), ID($sdffce), ID($dlatch), ID($adlatch), ID($ff)))
 			{
 				output = cell->getPort(ID::Q);
-				if (cell->type == ID($adff))
+				if (cell->type.in(ID($adff), ID($adffe), ID($adlatch)))
 					inputs.push_back(cell->getParam(ID::ARST_VALUE));
+				if (cell->type.in(ID($sdff), ID($sdffe), ID($sdffce)))
+					inputs.push_back(cell->getParam(ID::SRST_VALUE));
 				inputs.push_back(cell->getPort(ID::D));
 			}
 
diff --git a/passes/opt/wreduce.cc b/passes/opt/wreduce.cc
index 8ce2fd478..78e2bcbea 100644
--- a/passes/opt/wreduce.cc
+++ b/passes/opt/wreduce.cc
@@ -39,7 +39,8 @@ struct WreduceConfig
 			ID($lt), ID($le), ID($eq), ID($ne), ID($eqx), ID($nex), ID($ge), ID($gt),
 			ID($add), ID($sub), ID($mul), // ID($div), ID($mod), ID($divfloor), ID($modfloor), ID($pow),
 			ID($mux), ID($pmux),
-			ID($dff), ID($adff)
+			ID($dff), ID($dffe), ID($adff), ID($adffe), ID($sdff), ID($sdffe), ID($sdffce),
+			ID($dlatch), ID($adlatch),
 		});
 	}
 };
@@ -143,8 +144,8 @@ struct WreduceWorker
 
 		SigSpec sig_d = mi.sigmap(cell->getPort(ID::D));
 		SigSpec sig_q = mi.sigmap(cell->getPort(ID::Q));
-		bool is_adff = (cell->type == ID($adff));
-		Const initval, arst_value;
+		bool has_reset = false;
+		Const initval, rst_value;
 
 		int width_before = GetSize(sig_q);
 
@@ -152,7 +153,11 @@ struct WreduceWorker
 			return;
 
 		if (cell->parameters.count(ID::ARST_VALUE)) {
-			arst_value = cell->parameters[ID::ARST_VALUE];
+			rst_value = cell->parameters[ID::ARST_VALUE];
+			has_reset = true;
+		} else if (cell->parameters.count(ID::SRST_VALUE)) {
+			rst_value = cell->parameters[ID::SRST_VALUE];
+			has_reset = true;
 		}
 
 		bool zero_ext = sig_d[GetSize(sig_d)-1] == State::S0;
@@ -169,7 +174,7 @@ struct WreduceWorker
 		for (int i = GetSize(sig_q)-1; i >= 0; i--)
 		{
 			if (zero_ext && sig_d[i] == State::S0 && (initval[i] == State::S0 || initval[i] == State::Sx) &&
-					(!is_adff || i >= GetSize(arst_value) || arst_value[i] == State::S0 || arst_value[i] == State::Sx)) {
+					(!has_reset || i >= GetSize(rst_value) || rst_value[i] == State::S0 || rst_value[i] == State::Sx)) {
 				module->connect(sig_q[i], State::S0);
 				remove_init_bits.insert(sig_q[i]);
 				sig_d.remove(i);
@@ -178,7 +183,7 @@ struct WreduceWorker
 			}
 
 			if (sign_ext && i > 0 && sig_d[i] == sig_d[i-1] && initval[i] == initval[i-1] &&
-					(!is_adff || i >= GetSize(arst_value) || arst_value[i] == arst_value[i-1])) {
+					(!has_reset || i >= GetSize(rst_value) || rst_value[i] == rst_value[i-1])) {
 				module->connect(sig_q[i], sig_q[i-1]);
 				remove_init_bits.insert(sig_q[i]);
 				sig_d.remove(i);
@@ -221,8 +226,11 @@ struct WreduceWorker
 
 		// Narrow ARST_VALUE parameter to new size.
 		if (cell->parameters.count(ID::ARST_VALUE)) {
-			arst_value.bits.resize(GetSize(sig_q));
-			cell->setParam(ID::ARST_VALUE, arst_value);
+			rst_value.bits.resize(GetSize(sig_q));
+			cell->setParam(ID::ARST_VALUE, rst_value);
+		} else if (cell->parameters.count(ID::SRST_VALUE)) {
+			rst_value.bits.resize(GetSize(sig_q));
+			cell->setParam(ID::SRST_VALUE, rst_value);
 		}
 
 		cell->setPort(ID::D, sig_d);
@@ -272,7 +280,7 @@ struct WreduceWorker
 		if (cell->type.in(ID($mux), ID($pmux)))
 			return run_cell_mux(cell);
 
-		if (cell->type.in(ID($dff), ID($adff)))
+		if (cell->type.in(ID($dff), ID($dffe), ID($adff), ID($adffe), ID($sdff), ID($sdffe), ID($sdffce), ID($dlatch), ID($adlatch)))
 			return run_cell_dff(cell);
 
 		SigSpec sig = mi.sigmap(cell->getPort(ID::Y));
diff --git a/passes/techmap/dff2dffe.cc b/passes/techmap/dff2dffe.cc
index 36e2854c0..62ee3fea6 100644
--- a/passes/techmap/dff2dffe.cc
+++ b/passes/techmap/dff2dffe.cc
@@ -282,9 +282,9 @@ struct Dff2dffePass : public Pass {
 		log("\n");
 		log("    -direct-match <pattern>\n");
 		log("        like -direct for all DFF cell types matching the expression.\n");
-		log("        this will use $__DFFE_* as <external_gate_type> matching the\n");
-		log("        internal gate type $_DFF_*_, and $__DFFSE_* for those matching\n");
-		log("        $_DFFS_*_, except for $_DFF_[NP]_, which is converted to \n");
+		log("        this will use $_DFFE_* as <external_gate_type> matching the\n");
+		log("        internal gate type $_DFF_*_, and $_SDFFE_* for those matching\n");
+		log("        $_SDFF_*_, except for $_DFF_[NP]_, which is converted to \n");
 		log("        $_DFFE_[NP]_.\n");
 		log("\n");
 	}
@@ -318,23 +318,23 @@ struct Dff2dffePass : public Pass {
 				const char *pattern = args[++argidx].c_str();
 				if (patmatch(pattern, "$_DFF_P_"  )) found_match = true, direct_dict[ID($_DFF_P_)  ] = ID($_DFFE_PP_);
 				if (patmatch(pattern, "$_DFF_N_"  )) found_match = true, direct_dict[ID($_DFF_N_)  ] = ID($_DFFE_NP_);
-				if (patmatch(pattern, "$_DFF_NN0_")) found_match = true, direct_dict[ID($_DFF_NN0_)] = ID($__DFFE_NN0);
-				if (patmatch(pattern, "$_DFF_NN1_")) found_match = true, direct_dict[ID($_DFF_NN1_)] = ID($__DFFE_NN1);
-				if (patmatch(pattern, "$_DFF_NP0_")) found_match = true, direct_dict[ID($_DFF_NP0_)] = ID($__DFFE_NP0);
-				if (patmatch(pattern, "$_DFF_NP1_")) found_match = true, direct_dict[ID($_DFF_NP1_)] = ID($__DFFE_NP1);
-				if (patmatch(pattern, "$_DFF_PN0_")) found_match = true, direct_dict[ID($_DFF_PN0_)] = ID($__DFFE_PN0);
-				if (patmatch(pattern, "$_DFF_PN1_")) found_match = true, direct_dict[ID($_DFF_PN1_)] = ID($__DFFE_PN1);
-				if (patmatch(pattern, "$_DFF_PP0_")) found_match = true, direct_dict[ID($_DFF_PP0_)] = ID($__DFFE_PP0);
-				if (patmatch(pattern, "$_DFF_PP1_")) found_match = true, direct_dict[ID($_DFF_PP1_)] = ID($__DFFE_PP1);
-
-				if (patmatch(pattern, "$__DFFS_NN0_")) found_match = true, direct_dict[ID($__DFFS_NN0_)] = ID($__DFFSE_NN0);
-				if (patmatch(pattern, "$__DFFS_NN1_")) found_match = true, direct_dict[ID($__DFFS_NN1_)] = ID($__DFFSE_NN1);
-				if (patmatch(pattern, "$__DFFS_NP0_")) found_match = true, direct_dict[ID($__DFFS_NP0_)] = ID($__DFFSE_NP0);
-				if (patmatch(pattern, "$__DFFS_NP1_")) found_match = true, direct_dict[ID($__DFFS_NP1_)] = ID($__DFFSE_NP1);
-				if (patmatch(pattern, "$__DFFS_PN0_")) found_match = true, direct_dict[ID($__DFFS_PN0_)] = ID($__DFFSE_PN0);
-				if (patmatch(pattern, "$__DFFS_PN1_")) found_match = true, direct_dict[ID($__DFFS_PN1_)] = ID($__DFFSE_PN1);
-				if (patmatch(pattern, "$__DFFS_PP0_")) found_match = true, direct_dict[ID($__DFFS_PP0_)] = ID($__DFFSE_PP0);
-				if (patmatch(pattern, "$__DFFS_PP1_")) found_match = true, direct_dict[ID($__DFFS_PP1_)] = ID($__DFFSE_PP1);
+				if (patmatch(pattern, "$_DFF_NN0_")) found_match = true, direct_dict[ID($_DFF_NN0_)] = ID($_DFFE_NN0P_);
+				if (patmatch(pattern, "$_DFF_NN1_")) found_match = true, direct_dict[ID($_DFF_NN1_)] = ID($_DFFE_NN1P_);
+				if (patmatch(pattern, "$_DFF_NP0_")) found_match = true, direct_dict[ID($_DFF_NP0_)] = ID($_DFFE_NP0P_);
+				if (patmatch(pattern, "$_DFF_NP1_")) found_match = true, direct_dict[ID($_DFF_NP1_)] = ID($_DFFE_NP1P_);
+				if (patmatch(pattern, "$_DFF_PN0_")) found_match = true, direct_dict[ID($_DFF_PN0_)] = ID($_DFFE_PN0P_);
+				if (patmatch(pattern, "$_DFF_PN1_")) found_match = true, direct_dict[ID($_DFF_PN1_)] = ID($_DFFE_PN1P_);
+				if (patmatch(pattern, "$_DFF_PP0_")) found_match = true, direct_dict[ID($_DFF_PP0_)] = ID($_DFFE_PP0P_);
+				if (patmatch(pattern, "$_DFF_PP1_")) found_match = true, direct_dict[ID($_DFF_PP1_)] = ID($_DFFE_PP1P_);
+
+				if (patmatch(pattern, "$_SDFF_NN0_")) found_match = true, direct_dict[ID($_SDFF_NN0_)] = ID($_SDFFE_NN0P_);
+				if (patmatch(pattern, "$_SDFF_NN1_")) found_match = true, direct_dict[ID($_SDFF_NN1_)] = ID($_SDFFE_NN1P_);
+				if (patmatch(pattern, "$_SDFF_NP0_")) found_match = true, direct_dict[ID($_SDFF_NP0_)] = ID($_SDFFE_NP0P_);
+				if (patmatch(pattern, "$_SDFF_NP1_")) found_match = true, direct_dict[ID($_SDFF_NP1_)] = ID($_SDFFE_NP1P_);
+				if (patmatch(pattern, "$_SDFF_PN0_")) found_match = true, direct_dict[ID($_SDFF_PN0_)] = ID($_SDFFE_PN0P_);
+				if (patmatch(pattern, "$_SDFF_PN1_")) found_match = true, direct_dict[ID($_SDFF_PN1_)] = ID($_SDFFE_PN1P_);
+				if (patmatch(pattern, "$_SDFF_PP0_")) found_match = true, direct_dict[ID($_SDFF_PP0_)] = ID($_SDFFE_PP0P_);
+				if (patmatch(pattern, "$_SDFF_PP1_")) found_match = true, direct_dict[ID($_SDFF_PP1_)] = ID($_SDFFE_PP1P_);
 				if (!found_match)
 					log_cmd_error("No cell types matched pattern '%s'.\n", pattern);
 				continue;
diff --git a/passes/techmap/dff2dffs.cc b/passes/techmap/dff2dffs.cc
index 1cb923445..6c2cca4bc 100644
--- a/passes/techmap/dff2dffs.cc
+++ b/passes/techmap/dff2dffs.cc
@@ -31,7 +31,7 @@ struct Dff2dffsPass : public Pass {
 		log("\n");
 		log("    dff2dffs [options] [selection]\n");
 		log("\n");
-		log("Merge synchronous set/reset $_MUX_ cells to create $__DFFS_[NP][NP][01], to be run before\n");
+		log("Merge synchronous set/reset $_MUX_ cells to create $_SDFF_[NP][NP][01]_, to be run before\n");
 		log("dff2dffe for SR over CE priority.\n");
 		log("\n");
 		log("    -match-init\n");
@@ -138,21 +138,21 @@ struct Dff2dffsPass : public Pass {
 
 				if (sr_val == State::S1) {
 					if (cell->type == ID($_DFF_N_)) {
-						if (invert_sr) cell->type = ID($__DFFS_NN1_);
-						else cell->type = ID($__DFFS_NP1_);
+						if (invert_sr) cell->type = ID($_SDFF_NN1_);
+						else cell->type = ID($_SDFF_NP1_);
 					} else {
 						log_assert(cell->type == ID($_DFF_P_));
-						if (invert_sr) cell->type = ID($__DFFS_PN1_);
-						else cell->type = ID($__DFFS_PP1_);
+						if (invert_sr) cell->type = ID($_SDFF_PN1_);
+						else cell->type = ID($_SDFF_PP1_);
 					}
 				} else {
 					if (cell->type == ID($_DFF_N_)) {
-						if (invert_sr) cell->type = ID($__DFFS_NN0_);
-						else cell->type = ID($__DFFS_NP0_);
+						if (invert_sr) cell->type = ID($_SDFF_NN0_);
+						else cell->type = ID($_SDFF_NP0_);
 					} else {
 						log_assert(cell->type == ID($_DFF_P_));
-						if (invert_sr) cell->type = ID($__DFFS_PN0_);
-						else cell->type = ID($__DFFS_PP0_);
+						if (invert_sr) cell->type = ID($_SDFF_PN0_);
+						else cell->type = ID($_SDFF_PP0_);
 					}
 				}
 				cell->setPort(ID::R, sr_sig);
diff --git a/passes/techmap/simplemap.cc b/passes/techmap/simplemap.cc
index 3c78fbdbf..c8388e2d7 100644
--- a/passes/techmap/simplemap.cc
+++ b/passes/techmap/simplemap.cc
@@ -474,29 +474,93 @@ void simplemap_dffsr(RTLIL::Module *module, RTLIL::Cell *cell)
 	}
 }
 
-void simplemap_adff(RTLIL::Module *module, RTLIL::Cell *cell)
+void simplemap_dffsre(RTLIL::Module *module, RTLIL::Cell *cell)
 {
 	int width = cell->parameters.at(ID::WIDTH).as_int();
 	char clk_pol = cell->parameters.at(ID::CLK_POLARITY).as_bool() ? 'P' : 'N';
-	char rst_pol = cell->parameters.at(ID::ARST_POLARITY).as_bool() ? 'P' : 'N';
+	char set_pol = cell->parameters.at(ID::SET_POLARITY).as_bool() ? 'P' : 'N';
+	char clr_pol = cell->parameters.at(ID::CLR_POLARITY).as_bool() ? 'P' : 'N';
+	char en_pol = cell->parameters.at(ID::EN_POLARITY).as_bool() ? 'P' : 'N';
 
-	std::vector<RTLIL::State> rst_val = cell->parameters.at(ID::ARST_VALUE).bits;
+	RTLIL::SigSpec sig_clk = cell->getPort(ID::CLK);
+	RTLIL::SigSpec sig_s = cell->getPort(ID::SET);
+	RTLIL::SigSpec sig_r = cell->getPort(ID::CLR);
+	RTLIL::SigSpec sig_e = cell->getPort(ID::EN);
+	RTLIL::SigSpec sig_d = cell->getPort(ID::D);
+	RTLIL::SigSpec sig_q = cell->getPort(ID::Q);
+
+	IdString gate_type = stringf("$_DFFSR_%c%c%c%c_", clk_pol, set_pol, clr_pol, en_pol);
+
+	for (int i = 0; i < width; i++) {
+		RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type);
+		gate->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src));
+		gate->setPort(ID::C, sig_clk);
+		gate->setPort(ID::S, sig_s[i]);
+		gate->setPort(ID::R, sig_r[i]);
+		gate->setPort(ID::E, sig_e);
+		gate->setPort(ID::D, sig_d[i]);
+		gate->setPort(ID::Q, sig_q[i]);
+	}
+}
+
+void simplemap_adff_sdff(RTLIL::Module *module, RTLIL::Cell *cell)
+{
+	int width = cell->parameters.at(ID::WIDTH).as_int();
+	bool is_async = cell->type == ID($adff);
+	char clk_pol = cell->parameters.at(ID::CLK_POLARITY).as_bool() ? 'P' : 'N';
+	char rst_pol = cell->parameters.at(is_async ? ID::ARST_POLARITY : ID::SRST_POLARITY).as_bool() ? 'P' : 'N';
+	const char *type = is_async ? "DFF" : "SDFF";
+
+	std::vector<RTLIL::State> rst_val = cell->parameters.at(is_async ? ID::ARST_VALUE : ID::SRST_VALUE).bits;
 	while (int(rst_val.size()) < width)
 		rst_val.push_back(RTLIL::State::S0);
 
 	RTLIL::SigSpec sig_clk = cell->getPort(ID::CLK);
-	RTLIL::SigSpec sig_rst = cell->getPort(ID::ARST);
+	RTLIL::SigSpec sig_rst = cell->getPort(is_async ? ID::ARST : ID::SRST);
+	RTLIL::SigSpec sig_d = cell->getPort(ID::D);
+	RTLIL::SigSpec sig_q = cell->getPort(ID::Q);
+
+	IdString gate_type_0 = stringf("$_%s_%c%c0_", type, clk_pol, rst_pol);
+	IdString gate_type_1 = stringf("$_%s_%c%c1_", type, clk_pol, rst_pol);
+
+	for (int i = 0; i < width; i++) {
+		RTLIL::Cell *gate = module->addCell(NEW_ID, rst_val.at(i) == RTLIL::State::S1 ? gate_type_1 : gate_type_0);
+		gate->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src));
+		gate->setPort(ID::C, sig_clk);
+		gate->setPort(ID::R, sig_rst);
+		gate->setPort(ID::D, sig_d[i]);
+		gate->setPort(ID::Q, sig_q[i]);
+	}
+}
+
+void simplemap_adffe_sdffe_sdffce(RTLIL::Module *module, RTLIL::Cell *cell)
+{
+	int width = cell->parameters.at(ID::WIDTH).as_int();
+	bool is_async = cell->type == ID($adffe);
+	char clk_pol = cell->parameters.at(ID::CLK_POLARITY).as_bool() ? 'P' : 'N';
+	char rst_pol = cell->parameters.at(is_async ? ID::ARST_POLARITY : ID::SRST_POLARITY).as_bool() ? 'P' : 'N';
+	char en_pol = cell->parameters.at(ID::EN_POLARITY).as_bool() ? 'P' : 'N';
+	const char *type = is_async ? "DFFE" : cell->type == ID($sdffe) ? "SDFFE" : "SDFFCE";
+
+	std::vector<RTLIL::State> rst_val = cell->parameters.at(is_async ? ID::ARST_VALUE : ID::SRST_VALUE).bits;
+	while (int(rst_val.size()) < width)
+		rst_val.push_back(RTLIL::State::S0);
+
+	RTLIL::SigSpec sig_clk = cell->getPort(ID::CLK);
+	RTLIL::SigSpec sig_rst = cell->getPort(is_async ? ID::ARST : ID::SRST);
+	RTLIL::SigSpec sig_e = cell->getPort(ID::EN);
 	RTLIL::SigSpec sig_d = cell->getPort(ID::D);
 	RTLIL::SigSpec sig_q = cell->getPort(ID::Q);
 
-	IdString gate_type_0 = stringf("$_DFF_%c%c0_", clk_pol, rst_pol);
-	IdString gate_type_1 = stringf("$_DFF_%c%c1_", clk_pol, rst_pol);
+	IdString gate_type_0 = stringf("$_%s_%c%c0%c_", type, clk_pol, rst_pol, en_pol);
+	IdString gate_type_1 = stringf("$_%s_%c%c1%c_", type, clk_pol, rst_pol, en_pol);
 
 	for (int i = 0; i < width; i++) {
 		RTLIL::Cell *gate = module->addCell(NEW_ID, rst_val.at(i) == RTLIL::State::S1 ? gate_type_1 : gate_type_0);
 		gate->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src));
 		gate->setPort(ID::C, sig_clk);
 		gate->setPort(ID::R, sig_rst);
+		gate->setPort(ID::E, sig_e);
 		gate->setPort(ID::D, sig_d[i]);
 		gate->setPort(ID::Q, sig_q[i]);
 	}
@@ -522,6 +586,60 @@ void simplemap_dlatch(RTLIL::Module *module, RTLIL::Cell *cell)
 	}
 }
 
+void simplemap_adlatch(RTLIL::Module *module, RTLIL::Cell *cell)
+{
+	int width = cell->parameters.at(ID::WIDTH).as_int();
+	char en_pol = cell->parameters.at(ID::EN_POLARITY).as_bool() ? 'P' : 'N';
+	char rst_pol = cell->parameters.at(ID::ARST_POLARITY).as_bool() ? 'P' : 'N';
+
+	std::vector<RTLIL::State> rst_val = cell->parameters.at(ID::ARST_VALUE).bits;
+	while (int(rst_val.size()) < width)
+		rst_val.push_back(RTLIL::State::S0);
+
+	RTLIL::SigSpec sig_en = cell->getPort(ID::EN);
+	RTLIL::SigSpec sig_rst = cell->getPort(ID::ARST);
+	RTLIL::SigSpec sig_d = cell->getPort(ID::D);
+	RTLIL::SigSpec sig_q = cell->getPort(ID::Q);
+
+	IdString gate_type_0 = stringf("$_DLATCH_%c%c0_", en_pol, rst_pol);
+	IdString gate_type_1 = stringf("$_DLATCH_%c%c1_", en_pol, rst_pol);
+
+	for (int i = 0; i < width; i++) {
+		RTLIL::Cell *gate = module->addCell(NEW_ID, rst_val.at(i) == RTLIL::State::S1 ? gate_type_1 : gate_type_0);
+		gate->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src));
+		gate->setPort(ID::E, sig_en);
+		gate->setPort(ID::R, sig_rst);
+		gate->setPort(ID::D, sig_d[i]);
+		gate->setPort(ID::Q, sig_q[i]);
+	}
+}
+
+void simplemap_dlatchsr(RTLIL::Module *module, RTLIL::Cell *cell)
+{
+	int width = cell->parameters.at(ID::WIDTH).as_int();
+	char en_pol = cell->parameters.at(ID::EN_POLARITY).as_bool() ? 'P' : 'N';
+	char set_pol = cell->parameters.at(ID::SET_POLARITY).as_bool() ? 'P' : 'N';
+	char clr_pol = cell->parameters.at(ID::CLR_POLARITY).as_bool() ? 'P' : 'N';
+
+	RTLIL::SigSpec sig_en = cell->getPort(ID::EN);
+	RTLIL::SigSpec sig_s = cell->getPort(ID::SET);
+	RTLIL::SigSpec sig_r = cell->getPort(ID::CLR);
+	RTLIL::SigSpec sig_d = cell->getPort(ID::D);
+	RTLIL::SigSpec sig_q = cell->getPort(ID::Q);
+
+	IdString gate_type = stringf("$_DLATCHSR_%c%c%c_", en_pol, set_pol, clr_pol);
+
+	for (int i = 0; i < width; i++) {
+		RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type);
+		gate->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src));
+		gate->setPort(ID::E, sig_en);
+		gate->setPort(ID::S, sig_s[i]);
+		gate->setPort(ID::R, sig_r[i]);
+		gate->setPort(ID::D, sig_d[i]);
+		gate->setPort(ID::Q, sig_q[i]);
+	}
+}
+
 void simplemap_get_mappers(dict<IdString, void(*)(RTLIL::Module*, RTLIL::Cell*)> &mappers)
 {
 	mappers[ID($not)]         = simplemap_not;
@@ -553,8 +671,15 @@ void simplemap_get_mappers(dict<IdString, void(*)(RTLIL::Module*, RTLIL::Cell*)>
 	mappers[ID($dff)]         = simplemap_dff;
 	mappers[ID($dffe)]        = simplemap_dffe;
 	mappers[ID($dffsr)]       = simplemap_dffsr;
-	mappers[ID($adff)]        = simplemap_adff;
+	mappers[ID($dffsre)]      = simplemap_dffsre;
+	mappers[ID($adff)]        = simplemap_adff_sdff;
+	mappers[ID($sdff)]        = simplemap_adff_sdff;
+	mappers[ID($adffe)]       = simplemap_adffe_sdffe_sdffce;
+	mappers[ID($sdffe)]       = simplemap_adffe_sdffe_sdffce;
+	mappers[ID($sdffce)]      = simplemap_adffe_sdffe_sdffce;
 	mappers[ID($dlatch)]      = simplemap_dlatch;
+	mappers[ID($adlatch)]     = simplemap_adlatch;
+	mappers[ID($dlatchsr)]    = simplemap_dlatchsr;
 }
 
 void simplemap(RTLIL::Module *module, RTLIL::Cell *cell)
@@ -587,7 +712,7 @@ struct SimplemapPass : public Pass {
 		log("  $not, $pos, $and, $or, $xor, $xnor\n");
 		log("  $reduce_and, $reduce_or, $reduce_xor, $reduce_xnor, $reduce_bool\n");
 		log("  $logic_not, $logic_and, $logic_or, $mux, $tribuf\n");
-		log("  $sr, $ff, $dff, $dffsr, $adff, $dlatch\n");
+		log("  $sr, $ff, $dff, $dffe, $dffsr, $dffsre, $adff, $adffe, $sdff, $sdffe, $sdffce, $dlatch, $adlatch, $dlatchsr\n");
 		log("\n");
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
diff --git a/passes/techmap/zinit.cc b/passes/techmap/zinit.cc
index c0faa1f31..cc0b26bcc 100644
--- a/passes/techmap/zinit.cc
+++ b/passes/techmap/zinit.cc
@@ -91,20 +91,29 @@ struct ZinitPass : public Pass {
 								// FIXME: It would appear that supporting
 								//    $dffsr/$_DFFSR_* would require a new
 								//    cell type where S has priority over R
-				ID($ff), ID($dff), ID($dffe), /*ID($dffsr),*/ ID($adff),
+				ID($ff), ID($dff), ID($dffe), /*ID($dffsr),*/ ID($adff), ID($adffe),
+				ID($sdff), ID($sdffe), ID($sdffce),
 				ID($_FF_), ID($_DFFE_NN_), ID($_DFFE_NP_), ID($_DFFE_PN_), ID($_DFFE_PP_),
 				/*ID($_DFFSR_NNN_), ID($_DFFSR_NNP_), ID($_DFFSR_NPN_), ID($_DFFSR_NPP_),
 				ID($_DFFSR_PNN_), ID($_DFFSR_PNP_), ID($_DFFSR_PPN_), ID($_DFFSR_PPP_),*/
 				ID($_DFF_N_), ID($_DFF_NN0_), ID($_DFF_NN1_), ID($_DFF_NP0_), ID($_DFF_NP1_),
 				ID($_DFF_P_), ID($_DFF_PN0_), ID($_DFF_PN1_), ID($_DFF_PP0_), ID($_DFF_PP1_),
 				// Async set/reset
-				ID($__DFFE_NN0), ID($__DFFE_NN1), ID($__DFFE_NP0), ID($__DFFE_NP1),
-				ID($__DFFE_PN0), ID($__DFFE_PN1), ID($__DFFE_PP0), ID($__DFFE_PP1),
+				ID($_DFFE_NN0P_), ID($_DFFE_NN1P_), ID($_DFFE_NP0P_), ID($_DFFE_NP1P_),
+				ID($_DFFE_PN0P_), ID($_DFFE_PN1P_), ID($_DFFE_PP0P_), ID($_DFFE_PP1P_),
+				ID($_DFFE_NN0N_), ID($_DFFE_NN1N_), ID($_DFFE_NP0N_), ID($_DFFE_NP1N_),
+				ID($_DFFE_PN0N_), ID($_DFFE_PN1N_), ID($_DFFE_PP0N_), ID($_DFFE_PP1N_),
 				// Sync set/reset
-				ID($__DFFS_NN0_), ID($__DFFS_NN1_), ID($__DFFS_NP0_), ID($__DFFS_NP1_),
-				ID($__DFFS_PN0_), ID($__DFFS_PN1_), ID($__DFFS_PP0_), ID($__DFFS_PP1_),
-				ID($__DFFSE_NN0), ID($__DFFSE_NN1), ID($__DFFSE_NP0), ID($__DFFSE_NP1),
-				ID($__DFFSE_PN0), ID($__DFFSE_PN1), ID($__DFFSE_PP0), ID($__DFFSE_PP1)
+				ID($_SDFF_NN0_), ID($_SDFF_NN1_), ID($_SDFF_NP0_), ID($_SDFF_NP1_),
+				ID($_SDFF_PN0_), ID($_SDFF_PN1_), ID($_SDFF_PP0_), ID($_SDFF_PP1_),
+				ID($_SDFFE_NN0P_), ID($_SDFFE_NN1P_), ID($_SDFFE_NP0P_), ID($_SDFFE_NP1P_),
+				ID($_SDFFE_PN0P_), ID($_SDFFE_PN1P_), ID($_SDFFE_PP0P_), ID($_SDFFE_PP1P_),
+				ID($_SDFFE_NN0N_), ID($_SDFFE_NN1N_), ID($_SDFFE_NP0N_), ID($_SDFFE_NP1N_),
+				ID($_SDFFE_PN0N_), ID($_SDFFE_PN1N_), ID($_SDFFE_PP0N_), ID($_SDFFE_PP1N_),
+				ID($_SDFFCE_NN0P_), ID($_SDFFCE_NN1P_), ID($_SDFFCE_NP0P_), ID($_SDFFCE_NP1P_),
+				ID($_SDFFCE_PN0P_), ID($_SDFFCE_PN1P_), ID($_SDFFCE_PP0P_), ID($_SDFFCE_PP1P_),
+				ID($_SDFFCE_NN0N_), ID($_SDFFCE_NN1N_), ID($_SDFFCE_NP0N_), ID($_SDFFCE_NP1N_),
+				ID($_SDFFCE_PN0N_), ID($_SDFFCE_PN1N_), ID($_SDFFCE_PP0N_), ID($_SDFFCE_PP1N_)
 			};
 
 			for (auto cell : module->selected_cells())
@@ -151,13 +160,20 @@ struct ZinitPass : public Pass {
 				cell->setPort(ID::D, sig_d);
 				cell->setPort(ID::Q, initwire);
 
-				if (cell->type == ID($adff)) {
+				if (cell->type.in(ID($adff), ID($adffe))) {
 					auto val = cell->getParam(ID::ARST_VALUE);
 					for (int i = 0; i < GetSize(initwire); i++)
 						if (initval[i] == State::S1)
 							val[i] = (val[i] == State::S1 ? State::S0 : State::S1);
 					cell->setParam(ID::ARST_VALUE, std::move(val));
 				}
+				else if (cell->type.in(ID($sdff), ID($sdffe), ID($sdffce))) {
+					auto val = cell->getParam(ID::SRST_VALUE);
+					for (int i = 0; i < GetSize(initwire); i++)
+						if (initval[i] == State::S1)
+							val[i] = (val[i] == State::S1 ? State::S0 : State::S1);
+					cell->setParam(ID::SRST_VALUE, std::move(val));
+				}
 				else if (initval == State::S1) {
 					std::string t = cell->type.str();
 					if (cell->type.in(ID($_DFF_NN0_), ID($_DFF_NN1_), ID($_DFF_NP0_), ID($_DFF_NP1_),
@@ -165,15 +181,29 @@ struct ZinitPass : public Pass {
 					{
 						t[8] = (t[8] == '0' ? '1' : '0');
 					}
-					else if (cell->type.in(ID($__DFFE_NN0), ID($__DFFE_NN1), ID($__DFFE_NP0), ID($__DFFE_NP1),
-								ID($__DFFE_PN0), ID($__DFFE_PN1), ID($__DFFE_PP0), ID($__DFFE_PP1),
-								ID($__DFFS_NN0_), ID($__DFFS_NN1_), ID($__DFFS_NP0_), ID($__DFFS_NP1_),
-								ID($__DFFS_PN0_), ID($__DFFS_PN1_), ID($__DFFS_PP0_), ID($__DFFS_PP1_)))
+					else if (cell->type.in(ID($_SDFF_NN0_), ID($_SDFF_NN1_), ID($_SDFF_NP0_), ID($_SDFF_NP1_),
+								ID($_SDFF_PN0_), ID($_SDFF_PN1_), ID($_SDFF_PP0_), ID($_SDFF_PP1_)))
+					{
+						t[9] = (t[9] == '0' ? '1' : '0');
+					}
+					else if (cell->type.in(ID($_DFFE_NN0P_), ID($_DFFE_NN1P_), ID($_DFFE_NP0P_), ID($_DFFE_NP1P_),
+								ID($_DFFE_PN0P_), ID($_DFFE_PN1P_), ID($_DFFE_PP0P_), ID($_DFFE_PP1P_),
+								ID($_DFFE_NN0N_), ID($_DFFE_NN1N_), ID($_DFFE_NP0N_), ID($_DFFE_NP1N_),
+								ID($_DFFE_PN0N_), ID($_DFFE_PN1N_), ID($_DFFE_PP0N_), ID($_DFFE_PP1N_)))
+					{
+						t[9] = (t[9] == '0' ? '1' : '0');
+					}
+					else if (cell->type.in(ID($_SDFFE_NN0P_), ID($_SDFFE_NN1P_), ID($_SDFFE_NP0P_), ID($_SDFFE_NP1P_),
+								ID($_SDFFE_PN0P_), ID($_SDFFE_PN1P_), ID($_SDFFE_PP0P_), ID($_SDFFE_PP1P_),
+								ID($_SDFFE_NN0N_), ID($_SDFFE_NN1N_), ID($_SDFFE_NP0N_), ID($_SDFFE_NP1N_),
+								ID($_SDFFE_PN0N_), ID($_SDFFE_PN1N_), ID($_SDFFE_PP0N_), ID($_SDFFE_PP1N_)))
 					{
 						t[10] = (t[10] == '0' ? '1' : '0');
 					}
-					else if (cell->type.in(ID($__DFFSE_NN0), ID($__DFFSE_NN1), ID($__DFFSE_NP0), ID($__DFFSE_NP1),
-								ID($__DFFSE_PN0), ID($__DFFSE_PN1), ID($__DFFSE_PP0), ID($__DFFSE_PP1)))
+					else if (cell->type.in(ID($_SDFFCE_NN0P_), ID($_SDFFCE_NN1P_), ID($_SDFFCE_NP0P_), ID($_SDFFCE_NP1P_),
+								ID($_SDFFCE_PN0P_), ID($_SDFFCE_PN1P_), ID($_SDFFCE_PP0P_), ID($_SDFFCE_PP1P_),
+								ID($_SDFFCE_NN0N_), ID($_SDFFCE_NN1N_), ID($_SDFFCE_NP0N_), ID($_SDFFCE_NP1N_),
+								ID($_SDFFCE_PN0N_), ID($_SDFFCE_PN1N_), ID($_SDFFCE_PP0N_), ID($_SDFFCE_PP1N_)))
 					{
 						t[11] = (t[11] == '0' ? '1' : '0');
 					}