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| author | Marcelina Kościelnicka <mwk@0x04.net> | 2022-06-16 06:04:04 +0200 |
|---|---|---|
| committer | Marcelina Kościelnicka <mwk@0x04.net> | 2022-06-16 08:14:08 +0200 |
| commit | 25a4cd7020c100838e359b393ffb545532e69101 (patch) | |
| tree | 7144e7bc8eaef07857ae85b5f1e6684b4e79f536 /passes | |
| parent | 3046a06490831b171a04b000f3676c5df0af68d5 (diff) | |
| download | yosys-25a4cd7020c100838e359b393ffb545532e69101.tar.gz yosys-25a4cd7020c100838e359b393ffb545532e69101.tar.bz2 yosys-25a4cd7020c100838e359b393ffb545532e69101.zip | |
memory_libmap: Fix params emitted for unused ports for consistency.
Diffstat (limited to 'passes')
| -rw-r--r-- | passes/memory/memory_libmap.cc | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/passes/memory/memory_libmap.cc b/passes/memory/memory_libmap.cc index 898e0af85..d77e4be30 100644 --- a/passes/memory/memory_libmap.cc +++ b/passes/memory/memory_libmap.cc @@ -1706,10 +1706,11 @@ void MemMapping::emit_port(const MemConfig &cfg, std::vector<Cell*> &cells, cons if (pdef.wrbe_separate) { cell->setPort(stringf("\\PORT_%s_WR_EN", name), State::S0); cell->setPort(stringf("\\PORT_%s_WR_BE", name), hw_wren); - cell->setParam(stringf("\\PORT_%s_WR_BE_WIDTH", name), GetSize(hw_wren)); + if (cfg.def->width_mode != WidthMode::Single) + cell->setParam(stringf("\\PORT_%s_WR_BE_WIDTH", name), GetSize(hw_wren)); } else { cell->setPort(stringf("\\PORT_%s_WR_EN", name), hw_wren); - if (cfg.def->byte != 0) + if (cfg.def->byte != 0 && cfg.def->width_mode != WidthMode::Single) cell->setParam(stringf("\\PORT_%s_WR_EN_WIDTH", name), GetSize(hw_wren)); } } |