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| author | Clifford Wolf <clifford@clifford.at> | 2019-09-20 10:27:17 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2019-09-20 10:27:17 +0200 |
| commit | 1f64b34c64eb4177139aab7b91bd6173c33923d1 (patch) | |
| tree | 5b09946c5d0b05f9853400f4654e6055bee2b371 /passes | |
| parent | db17833a5fa814fa8a871cf7a483802673b9b029 (diff) | |
| download | yosys-1f64b34c64eb4177139aab7b91bd6173c33923d1.tar.gz yosys-1f64b34c64eb4177139aab7b91bd6173c33923d1.tar.bz2 yosys-1f64b34c64eb4177139aab7b91bd6173c33923d1.zip | |
Add "add -mod"
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Diffstat (limited to 'passes')
| -rw-r--r-- | passes/cmds/add.cc | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/passes/cmds/add.cc b/passes/cmds/add.cc index af6f7043d..dd05ac81f 100644 --- a/passes/cmds/add.cc +++ b/passes/cmds/add.cc @@ -105,6 +105,11 @@ struct AddPass : public Pass { log("Like 'add -input', but also connect the signal between instances of the\n"); log("selected modules.\n"); log("\n"); + log("\n"); + log(" add -mod <name[s]>\n"); + log("\n"); + log("Add module[s] with the specified name[s].\n"); + log("\n"); } void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE { @@ -113,6 +118,7 @@ struct AddPass : public Pass { bool arg_flag_input = false; bool arg_flag_output = false; bool arg_flag_global = false; + bool mod_mode = false; int arg_width = 0; size_t argidx; @@ -133,8 +139,20 @@ struct AddPass : public Pass { arg_width = atoi(args[++argidx].c_str()); continue; } + if (arg == "-mod") { + mod_mode = true; + argidx++; + break; + } break; } + + if (mod_mode) { + for (; argidx < args.size(); argidx++) + design->addModule(RTLIL::escape_id(args[argidx])); + return; + } + extra_args(args, argidx, design); for (auto &mod : design->modules_) |