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| author | Clifford Wolf <clifford@clifford.at> | 2017-12-14 03:13:47 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2017-12-14 03:13:47 +0100 |
| commit | 162c29bd6b2ceebb0e9ce32dc45ab7ed18abd42e (patch) | |
| tree | cb155dd398365d47e48beb908678fc1db9233e08 /passes | |
| parent | a48ec49017a8a792841cf486167c643db23eeb22 (diff) | |
| parent | 9419de3e371451f7f0eb51e89cab3fa8bebba26c (diff) | |
| download | yosys-162c29bd6b2ceebb0e9ce32dc45ab7ed18abd42e.tar.gz yosys-162c29bd6b2ceebb0e9ce32dc45ab7ed18abd42e.tar.bz2 yosys-162c29bd6b2ceebb0e9ce32dc45ab7ed18abd42e.zip | |
Merge branch 'master' into btor-ng
Diffstat (limited to 'passes')
| -rw-r--r-- | passes/sat/clk2fflogic.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/sat/clk2fflogic.cc b/passes/sat/clk2fflogic.cc index d334cf7d9..7e952e99b 100644 --- a/passes/sat/clk2fflogic.cc +++ b/passes/sat/clk2fflogic.cc @@ -126,7 +126,7 @@ struct Clk2fflogicPass : public Pass { SigSpec clock_edge = module->Eqx(NEW_ID, {clk, SigSpec(past_clk)}, clock_edge_pattern); - SigSpec en_q = module->addWire(NEW_ID, GetSize(addr)); + SigSpec en_q = module->addWire(NEW_ID, GetSize(en)); module->addFf(NEW_ID, en, en_q); SigSpec addr_q = module->addWire(NEW_ID, GetSize(addr)); |