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| author | Clifford Wolf <clifford@clifford.at> | 2013-12-06 12:53:20 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2013-12-06 12:53:20 +0100 |
| commit | 06d96e8fcf651a3fd16f5c64cbb01570471c7c0e (patch) | |
| tree | 4c4fcdfcb8adbdec305a0b75f065f6578cbd6c70 /passes | |
| parent | 8311492475090451c7c69ef076809bb5e9852f9b (diff) | |
| download | yosys-06d96e8fcf651a3fd16f5c64cbb01570471c7c0e.tar.gz yosys-06d96e8fcf651a3fd16f5c64cbb01570471c7c0e.tar.bz2 yosys-06d96e8fcf651a3fd16f5c64cbb01570471c7c0e.zip | |
Fixes in fsm detect/extract for better detection of non-fsm circuits
Diffstat (limited to 'passes')
| -rw-r--r-- | passes/fsm/fsm_detect.cc | 2 | ||||
| -rw-r--r-- | passes/fsm/fsm_extract.cc | 6 |
2 files changed, 4 insertions, 4 deletions
diff --git a/passes/fsm/fsm_detect.cc b/passes/fsm/fsm_detect.cc index 6cd428a87..a8ec19126 100644 --- a/passes/fsm/fsm_detect.cc +++ b/passes/fsm/fsm_detect.cc @@ -161,7 +161,7 @@ struct FsmDetectPass : public Pass { sig_at_port.clear(); for (auto &cell_it : module->cells) for (auto &conn_it : cell_it.second->connections) { - if (ct.cell_output(cell_it.second->type, conn_it.first)) { + if (ct.cell_output(cell_it.second->type, conn_it.first) || !ct.cell_known(cell_it.second->type)) { RTLIL::SigSpec sig = conn_it.second; assign_map.apply(sig); sig2driver.insert(sig, sig2driver_entry_t(cell_it.second, conn_it.first)); diff --git a/passes/fsm/fsm_extract.cc b/passes/fsm/fsm_extract.cc index dc3a9ec09..9cba904a7 100644 --- a/passes/fsm/fsm_extract.cc +++ b/passes/fsm/fsm_extract.cc @@ -144,8 +144,8 @@ static void find_transitions(ConstEval &ce, ConstEval &ce_nostop, FsmData &fsm_d return; } - assert(undef.width > 0); - assert(ce.stop_signals.check_all(undef)); + log_assert(undef.width > 0); + log_assert(ce.stop_signals.check_all(undef)); undef = undef.extract(0, 1); constval = undef; @@ -361,7 +361,7 @@ struct FsmExtractPass : public Pass { sig2trigger.clear(); for (auto &cell_it : module->cells) for (auto &conn_it : cell_it.second->connections) { - if (ct.cell_output(cell_it.second->type, conn_it.first)) { + if (ct.cell_output(cell_it.second->type, conn_it.first) || !ct.cell_known(cell_it.second->type)) { RTLIL::SigSpec sig = conn_it.second; assign_map.apply(sig); sig2driver.insert(sig, sig2driver_entry_t(cell_it.first, conn_it.first)); |