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| author | Clifford Wolf <clifford@clifford.at> | 2014-01-03 17:50:39 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-01-03 17:50:39 +0100 |
| commit | 03f0ab9de29aa3e396c1b1b3e62e6676de3946a3 (patch) | |
| tree | eef7ad0b44adfad45befc9afe2057f9aa26c1365 /passes | |
| parent | 7354a1718e2e3f2eec4843a56410743af0ff7a83 (diff) | |
| download | yosys-03f0ab9de29aa3e396c1b1b3e62e6676de3946a3.tar.gz yosys-03f0ab9de29aa3e396c1b1b3e62e6676de3946a3.tar.bz2 yosys-03f0ab9de29aa3e396c1b1b3e62e6676de3946a3.zip | |
Cleanups in freduce command
Diffstat (limited to 'passes')
| -rw-r--r-- | passes/sat/freduce.cc | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/passes/sat/freduce.cc b/passes/sat/freduce.cc index 893fe5167..23ab8a04a 100644 --- a/passes/sat/freduce.cc +++ b/passes/sat/freduce.cc @@ -441,8 +441,6 @@ struct FreduceWorker int bits_count = 0; std::map<std::vector<RTLIL::SigBit>, std::vector<RTLIL::SigBit>> buckets; - buckets[std::vector<RTLIL::SigBit>()].push_back(RTLIL::SigBit(RTLIL::State::S0)); - buckets[std::vector<RTLIL::SigBit>()].push_back(RTLIL::SigBit(RTLIL::State::S1)); for (auto &batch : batches) { for (auto &bit : batch) @@ -464,6 +462,11 @@ struct FreduceWorker } log(" Sorted %d signal bits into %d buckets.\n", bits_count, int(buckets.size())); + if (buckets.count(std::vector<RTLIL::SigBit>()) != 0) { + buckets[std::vector<RTLIL::SigBit>()].push_back(RTLIL::SigBit(RTLIL::State::S0)); + buckets[std::vector<RTLIL::SigBit>()].push_back(RTLIL::SigBit(RTLIL::State::S1)); + } + std::vector<std::vector<equiv_bit_t>> equiv; for (auto &bucket : buckets) { |