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| author | Clifford Wolf <clifford@clifford.at> | 2014-07-31 16:38:54 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-07-31 16:38:54 +0200 |
| commit | cdae8abe16847c533171fed111beea7b52202cce (patch) | |
| tree | bf8dddb4a4ca4d70c83603ef61b2d22cb95d153a /passes/tests | |
| parent | b5a9e51b966abdfedc9309defa79b5141928e84a (diff) | |
| download | yosys-cdae8abe16847c533171fed111beea7b52202cce.tar.gz yosys-cdae8abe16847c533171fed111beea7b52202cce.tar.bz2 yosys-cdae8abe16847c533171fed111beea7b52202cce.zip | |
Renamed port access function on RTLIL::Cell, added param access functions
Diffstat (limited to 'passes/tests')
| -rw-r--r-- | passes/tests/test_cell.cc | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/passes/tests/test_cell.cc b/passes/tests/test_cell.cc index 4034f120e..946490135 100644 --- a/passes/tests/test_cell.cc +++ b/passes/tests/test_cell.cc @@ -38,7 +38,7 @@ static void create_gold_module(RTLIL::Design *design, std::string cell_type, std RTLIL::Wire *wire = module->addWire("\\A"); wire->width = 1 + xorshift32(8); wire->port_input = true; - cell->set("\\A", wire); + cell->setPort("\\A", wire); } if (cell_type_flags.find('B') != std::string::npos) { @@ -48,7 +48,7 @@ static void create_gold_module(RTLIL::Design *design, std::string cell_type, std else wire->width = 1 + xorshift32(8); wire->port_input = true; - cell->set("\\B", wire); + cell->setPort("\\B", wire); } if (cell_type_flags.find('S') != std::string::npos && xorshift32(2)) { @@ -69,7 +69,7 @@ static void create_gold_module(RTLIL::Design *design, std::string cell_type, std RTLIL::Wire *wire = module->addWire("\\Y"); wire->width = 1 + xorshift32(8); wire->port_output = true; - cell->set("\\Y", wire); + cell->setPort("\\Y", wire); } module->fixup_ports(); |