kernel: big fat patch to use more ID::*, otherwise ID(*)

3 files changed, 104 insertions, 104 deletions

diff --git a/passes/tests/test_abcloop.cc b/passes/tests/test_abcloop.cc
index 5d5466afe..894610e2b 100644
--- a/passes/tests/test_abcloop.cc
+++ b/passes/tests/test_abcloop.cc
@@ -55,7 +55,7 @@ static void test_abcloop()
 
 	while (1)
 	{
-		module = design->addModule("\\uut");
+		module = design->addModule(ID(UUT));
 		create_cycles++;
 
 		in_sig = {};
diff --git a/passes/tests/test_autotb.cc b/passes/tests/test_autotb.cc
index 2b6a86c25..1f071bd69 100644
--- a/passes/tests/test_autotb.cc
+++ b/passes/tests/test_autotb.cc
@@ -106,7 +106,7 @@ static void autotest(std::ostream &f, RTLIL::Design *design, int num_iter, int s
 
 		RTLIL::Module *mod = it->second;
 
-		if (mod->get_bool_attribute("\\gentb_skip"))
+		if (mod->get_bool_attribute(ID::gentb_skip))
 			continue;
 
 		int count_ports = 0;
@@ -119,7 +119,7 @@ static void autotest(std::ostream &f, RTLIL::Design *design, int num_iter, int s
 				f << stringf("wire [%d:0] %s;\n", wire->width-1, idy("sig", mod->name.str(), wire->name.str()).c_str());
 			} else if (wire->port_input) {
 				count_ports++;
-				bool is_clksignal = wire->get_bool_attribute("\\gentb_clock");
+				bool is_clksignal = wire->get_bool_attribute(ID::gentb_clock);
 				for (auto it3 = mod->processes.begin(); it3 != mod->processes.end(); ++it3)
 				for (auto it4 = it3->second->syncs.begin(); it4 != it3->second->syncs.end(); ++it4) {
 					if ((*it4)->type == RTLIL::ST0 || (*it4)->type == RTLIL::ST1)
@@ -129,12 +129,12 @@ static void autotest(std::ostream &f, RTLIL::Design *design, int num_iter, int s
 						if (c.wire == wire)
 							is_clksignal = true;
 				}
-				if (is_clksignal && wire->attributes.count("\\gentb_constant") == 0) {
+				if (is_clksignal && wire->attributes.count(ID::gentb_constant) == 0) {
 					signal_clk[idy("sig", mod->name.str(), wire->name.str())] = wire->width;
 				} else {
 					signal_in[idy("sig", mod->name.str(), wire->name.str())] = wire->width;
-					if (wire->attributes.count("\\gentb_constant") != 0)
-						signal_const[idy("sig", mod->name.str(), wire->name.str())] = wire->attributes["\\gentb_constant"].as_string();
+					if (wire->attributes.count(ID::gentb_constant) != 0)
+						signal_const[idy("sig", mod->name.str(), wire->name.str())] = wire->attributes[ID::gentb_constant].as_string();
 				}
 				f << stringf("reg [%d:0] %s;\n", wire->width-1, idy("sig", mod->name.str(), wire->name.str()).c_str());
 			}
@@ -313,7 +313,7 @@ static void autotest(std::ostream &f, RTLIL::Design *design, int num_iter, int s
 	f << stringf("\t// $dumpvars(0, testbench);\n");
 	f << stringf("\tfile = $fopen(`outfile);\n");
 	for (auto it = design->modules_.begin(); it != design->modules_.end(); ++it)
-		if (!it->second->get_bool_attribute("\\gentb_skip"))
+		if (!it->second->get_bool_attribute(ID::gentb_skip))
 			f << stringf("\t%s;\n", idy(it->first.str(), "test").c_str());
 	f << stringf("\t$fclose(file);\n");
 	f << stringf("\t$finish;\n");
diff --git a/passes/tests/test_cell.cc b/passes/tests/test_cell.cc
index ad169e70a..cdbe922b2 100644
--- a/passes/tests/test_cell.cc
+++ b/passes/tests/test_cell.cc
@@ -39,14 +39,14 @@ static uint32_t xorshift32(uint32_t limit) {
 
 static void create_gold_module(RTLIL::Design *design, RTLIL::IdString cell_type, std::string cell_type_flags, bool constmode, bool muxdiv)
 {
-	RTLIL::Module *module = design->addModule("\\gold");
-	RTLIL::Cell *cell = module->addCell("\\UUT", cell_type);
+	RTLIL::Module *module = design->addModule(ID(gold));
+	RTLIL::Cell *cell = module->addCell(ID(UUT), cell_type);
 	RTLIL::Wire *wire;
 
-	if (cell_type.in("$mux", "$pmux"))
+	if (cell_type.in(ID($mux), ID($pmux)))
 	{
 		int width = 1 + xorshift32(8);
-		int swidth = cell_type == "$mux" ? 1 : 1 + xorshift32(8);
+		int swidth = cell_type == ID($mux) ? 1 : 1 + xorshift32(8);
 
 		wire = module->addWire(ID::A);
 		wire->width = width;
@@ -69,7 +69,7 @@ static void create_gold_module(RTLIL::Design *design, RTLIL::IdString cell_type,
 		cell->setPort(ID::Y, wire);
 	}
 
-	if (cell_type == "$fa")
+	if (cell_type == ID($fa))
 	{
 		int width = 1 + xorshift32(8);
 
@@ -83,15 +83,15 @@ static void create_gold_module(RTLIL::Design *design, RTLIL::IdString cell_type,
 		wire->port_input = true;
 		cell->setPort(ID::B, wire);
 
-		wire = module->addWire("\\C");
+		wire = module->addWire(ID::C);
 		wire->width = width;
 		wire->port_input = true;
-		cell->setPort("\\C", wire);
+		cell->setPort(ID::C, wire);
 
-		wire = module->addWire("\\X");
+		wire = module->addWire(ID::X);
 		wire->width = width;
 		wire->port_output = true;
-		cell->setPort("\\X", wire);
+		cell->setPort(ID::X, wire);
 
 		wire = module->addWire(ID::Y);
 		wire->width = width;
@@ -99,31 +99,31 @@ static void create_gold_module(RTLIL::Design *design, RTLIL::IdString cell_type,
 		cell->setPort(ID::Y, wire);
 	}
 
-	if (cell_type == "$lcu")
+	if (cell_type == ID($lcu))
 	{
 		int width = 1 + xorshift32(8);
 
-		wire = module->addWire("\\P");
+		wire = module->addWire(ID::P);
 		wire->width = width;
 		wire->port_input = true;
-		cell->setPort("\\P", wire);
+		cell->setPort(ID::P, wire);
 
-		wire = module->addWire("\\G");
+		wire = module->addWire(ID::G);
 		wire->width = width;
 		wire->port_input = true;
-		cell->setPort("\\G", wire);
+		cell->setPort(ID::G, wire);
 
-		wire = module->addWire("\\CI");
+		wire = module->addWire(ID::CI);
 		wire->port_input = true;
-		cell->setPort("\\CI", wire);
+		cell->setPort(ID::CI, wire);
 
-		wire = module->addWire("\\CO");
+		wire = module->addWire(ID::CO);
 		wire->width = width;
 		wire->port_output = true;
-		cell->setPort("\\CO", wire);
+		cell->setPort(ID::CO, wire);
 	}
 
-	if (cell_type == "$macc")
+	if (cell_type == ID($macc))
 	{
 		Macc macc;
 		int width = 1 + xorshift32(8);
@@ -171,7 +171,7 @@ static void create_gold_module(RTLIL::Design *design, RTLIL::IdString cell_type,
 		macc.to_cell(cell);
 	}
 
-	if (cell_type == "$lut")
+	if (cell_type == ID($lut))
 	{
 		int width = 1 + xorshift32(6);
 
@@ -188,10 +188,10 @@ static void create_gold_module(RTLIL::Design *design, RTLIL::IdString cell_type,
 		for (int i = 0; i < (1 << width); i++)
 			config.append(xorshift32(2) ? State::S1 : State::S0);
 
-		cell->setParam("\\LUT", config.as_const());
+		cell->setParam(ID::LUT, config.as_const());
 	}
 
-	if (cell_type == "$sop")
+	if (cell_type == ID($sop))
 	{
 		int width = 1 + xorshift32(8);
 		int depth = 1 + xorshift32(8);
@@ -222,8 +222,8 @@ static void create_gold_module(RTLIL::Design *design, RTLIL::IdString cell_type,
 					break;
 			}
 
-		cell->setParam("\\DEPTH", depth);
-		cell->setParam("\\TABLE", config.as_const());
+		cell->setParam(ID::DEPTH, depth);
+		cell->setParam(ID::TABLE, config.as_const());
 	}
 
 	if (cell_type_flags.find('A') != std::string::npos) {
@@ -245,16 +245,16 @@ static void create_gold_module(RTLIL::Design *design, RTLIL::IdString cell_type,
 
 	if (cell_type_flags.find('S') != std::string::npos && xorshift32(2)) {
 		if (cell_type_flags.find('A') != std::string::npos)
-			cell->parameters["\\A_SIGNED"] = true;
+			cell->parameters[ID::A_SIGNED] = true;
 		if (cell_type_flags.find('B') != std::string::npos)
-			cell->parameters["\\B_SIGNED"] = true;
+			cell->parameters[ID::B_SIGNED] = true;
 	}
 
 	if (cell_type_flags.find('s') != std::string::npos) {
 		if (cell_type_flags.find('A') != std::string::npos && xorshift32(2))
-			cell->parameters["\\A_SIGNED"] = true;
+			cell->parameters[ID::A_SIGNED] = true;
 		if (cell_type_flags.find('B') != std::string::npos && xorshift32(2))
-			cell->parameters["\\B_SIGNED"] = true;
+			cell->parameters[ID::B_SIGNED] = true;
 	}
 
 	if (cell_type_flags.find('Y') != std::string::npos) {
@@ -264,32 +264,32 @@ static void create_gold_module(RTLIL::Design *design, RTLIL::IdString cell_type,
 		cell->setPort(ID::Y, wire);
 	}
 
-	if (muxdiv && cell_type.in("$div", "$mod")) {
+	if (muxdiv && cell_type.in(ID($div), ID($mod))) {
 		auto b_not_zero = module->ReduceBool(NEW_ID, cell->getPort(ID::B));
 		auto div_out = module->addWire(NEW_ID, GetSize(cell->getPort(ID::Y)));
 		module->addMux(NEW_ID, RTLIL::SigSpec(0, GetSize(div_out)), div_out, b_not_zero, cell->getPort(ID::Y));
 		cell->setPort(ID::Y, div_out);
 	}
 
-	if (cell_type == "$alu")
+	if (cell_type == ID($alu))
 	{
-		wire = module->addWire("\\CI");
+		wire = module->addWire(ID::CI);
 		wire->port_input = true;
-		cell->setPort("\\CI", wire);
+		cell->setPort(ID::CI, wire);
 
-		wire = module->addWire("\\BI");
+		wire = module->addWire(ID::BI);
 		wire->port_input = true;
-		cell->setPort("\\BI", wire);
+		cell->setPort(ID::BI, wire);
 
-		wire = module->addWire("\\X");
+		wire = module->addWire(ID::X);
 		wire->width = GetSize(cell->getPort(ID::Y));
 		wire->port_output = true;
-		cell->setPort("\\X", wire);
+		cell->setPort(ID::X, wire);
 
-		wire = module->addWire("\\CO");
+		wire = module->addWire(ID::CO);
 		wire->width = GetSize(cell->getPort(ID::Y));
 		wire->port_output = true;
-		cell->setPort("\\CO", wire);
+		cell->setPort(ID::CO, wire);
 	}
 
 	if (constmode)
@@ -421,8 +421,8 @@ static void run_eval_test(RTLIL::Design *design, bool verbose, bool nosat, std::
 {
 	log("Eval testing:%c", verbose ? '\n' : ' ');
 
-	RTLIL::Module *gold_mod = design->module("\\gold");
-	RTLIL::Module *gate_mod = design->module("\\gate");
+	RTLIL::Module *gold_mod = design->module(ID(gold));
+	RTLIL::Module *gate_mod = design->module(ID(gate));
 	ConstEval gold_ce(gold_mod), gate_ce(gate_mod);
 
 	ezSatPtr ez1, ez2;
@@ -800,65 +800,65 @@ struct TestCellPass : public Pass {
 			log("Rng seed value: %d\n", int(xorshift32_state));
 		}
 
-		std::map<std::string, std::string> cell_types;
-		std::vector<std::string> selected_cell_types;
-
-		cell_types["$not"] = "ASY";
-		cell_types["$pos"] = "ASY";
-		cell_types["$neg"] = "ASY";
-
-		cell_types["$and"]  = "ABSY";
-		cell_types["$or"]   = "ABSY";
-		cell_types["$xor"]  = "ABSY";
-		cell_types["$xnor"] = "ABSY";
-
-		cell_types["$reduce_and"]  = "ASY";
-		cell_types["$reduce_or"]   = "ASY";
-		cell_types["$reduce_xor"]  = "ASY";
-		cell_types["$reduce_xnor"] = "ASY";
-		cell_types["$reduce_bool"] = "ASY";
-
-		cell_types["$shl"]    = "ABshY";
-		cell_types["$shr"]    = "ABshY";
-		cell_types["$sshl"]   = "ABshY";
-		cell_types["$sshr"]   = "ABshY";
-		cell_types["$shift"]  = "ABshY";
-		cell_types["$shiftx"] = "ABshY";
-
-		cell_types["$lt"]  = "ABSY";
-		cell_types["$le"]  = "ABSY";
-		cell_types["$eq"]  = "ABSY";
-		cell_types["$ne"]  = "ABSY";
-		// cell_types["$eqx"] = "ABSY";
-		// cell_types["$nex"] = "ABSY";
-		cell_types["$ge"]  = "ABSY";
-		cell_types["$gt"]  = "ABSY";
-
-		cell_types["$add"] = "ABSY";
-		cell_types["$sub"] = "ABSY";
-		cell_types["$mul"] = "ABSY";
-		cell_types["$div"] = "ABSY";
-		cell_types["$mod"] = "ABSY";
-		// cell_types["$pow"] = "ABsY";
-
-		cell_types["$logic_not"] = "ASY";
-		cell_types["$logic_and"] = "ABSY";
-		cell_types["$logic_or"]  = "ABSY";
+		std::map<IdString, std::string> cell_types;
+		std::vector<IdString> selected_cell_types;
+
+		cell_types[ID($not)] = "ASY";
+		cell_types[ID($pos)] = "ASY";
+		cell_types[ID($neg)] = "ASY";
+
+		cell_types[ID($and)]  = "ABSY";
+		cell_types[ID($or)]   = "ABSY";
+		cell_types[ID($xor)]  = "ABSY";
+		cell_types[ID($xnor)] = "ABSY";
+
+		cell_types[ID($reduce_and)]  = "ASY";
+		cell_types[ID($reduce_or)]   = "ASY";
+		cell_types[ID($reduce_xor)]  = "ASY";
+		cell_types[ID($reduce_xnor)] = "ASY";
+		cell_types[ID($reduce_bool)] = "ASY";
+
+		cell_types[ID($shl)]    = "ABshY";
+		cell_types[ID($shr)]    = "ABshY";
+		cell_types[ID($sshl)]   = "ABshY";
+		cell_types[ID($sshr)]   = "ABshY";
+		cell_types[ID($shift)]  = "ABshY";
+		cell_types[ID($shiftx)] = "ABshY";
+
+		cell_types[ID($lt)]  = "ABSY";
+		cell_types[ID($le)]  = "ABSY";
+		cell_types[ID($eq)]  = "ABSY";
+		cell_types[ID($ne)]  = "ABSY";
+		// cell_types[ID($eqx)] = "ABSY";
+		// cell_types[ID($nex)] = "ABSY";
+		cell_types[ID($ge)]  = "ABSY";
+		cell_types[ID($gt)]  = "ABSY";
+
+		cell_types[ID($add)] = "ABSY";
+		cell_types[ID($sub)] = "ABSY";
+		cell_types[ID($mul)] = "ABSY";
+		cell_types[ID($div)] = "ABSY";
+		cell_types[ID($mod)] = "ABSY";
+		// cell_types[ID($pow)] = "ABsY";
+
+		cell_types[ID($logic_not)] = "ASY";
+		cell_types[ID($logic_and)] = "ABSY";
+		cell_types[ID($logic_or)]  = "ABSY";
 
 		if (edges) {
-			cell_types["$mux"] = "*";
-			cell_types["$pmux"] = "*";
+			cell_types[ID($mux)] = "*";
+			cell_types[ID($pmux)] = "*";
 		}
 
-		// cell_types["$slice"] = "A";
-		// cell_types["$concat"] = "A";
+		// cell_types[ID($slice)] = "A";
+		// cell_types[ID($concat)] = "A";
 
-		cell_types["$lut"] = "*";
-		cell_types["$sop"] = "*";
-		cell_types["$alu"] = "ABSY";
-		cell_types["$lcu"] = "*";
-		cell_types["$macc"] = "*";
-		cell_types["$fa"] = "*";
+		cell_types[ID($lut)] = "*";
+		cell_types[ID($sop)] = "*";
+		cell_types[ID($alu)] = "ABSY";
+		cell_types[ID($lcu)] = "*";
+		cell_types[ID($macc)] = "*";
+		cell_types[ID($fa)] = "*";
 
 		for (; argidx < GetSize(args); argidx++)
 		{
@@ -873,7 +873,7 @@ struct TestCellPass : public Pass {
 			}
 
 			if (args[argidx].compare(0, 1, "/") == 0) {
-				std::vector<std::string> new_selected_cell_types;
+				std::vector<IdString> new_selected_cell_types;
 				for (auto it : selected_cell_types)
 					if (it != args[argidx].substr(1))
 						new_selected_cell_types.push_back(it);
@@ -886,10 +886,10 @@ struct TestCellPass : public Pass {
 				int charcount = 100;
 				for (auto &it : cell_types) {
 					if (charcount > 60) {
-						cell_type_list += "\n" + it.first;
+						cell_type_list += stringf("\n%s", + log_id(it.first));
 						charcount = 0;
 					} else
-						cell_type_list += " " + it.first;
+						cell_type_list += stringf(" %s", log_id(it.first));
 					charcount += GetSize(it.first);
 				}
 				log_cmd_error("The cell type `%s' is currently not supported. Try one of these:%s\n",