Added "test_cell -w" feature

1 files changed, 39 insertions, 18 deletions

diff --git a/passes/tests/test_cell.cc b/passes/tests/test_cell.cc
index 3406d7e3e..f0d19b6bb 100644
--- a/passes/tests/test_cell.cc
+++ b/passes/tests/test_cell.cc
@@ -508,7 +508,7 @@ struct TestCellPass : public Pass {
 		log("by comparing SAT solver, EVAL and TECHMAP implementations of the cell types..\n");
 		log("\n");
 		log("Run with 'all' instead of a cell type to run the test on all supported\n");
-		log("cell types.\n");
+		log("cell types. Use for example 'all /$add' for all cell types except $add.\n");
 		log("\n");
 		log("    -n {integer}\n");
 		log("        create this number of cell instances and test them (default = 100).\n");
@@ -519,6 +519,10 @@ struct TestCellPass : public Pass {
 		log("    -f {ilang_file}\n");
 		log("        don't generate circuits. instead load the specified ilang file.\n");
 		log("\n");
+		log("    -w {filename_prefix}\n");
+		log("        don't test anything. just generate the circuits and write them\n");
+		log("        to ilang files with the specified prefix\n");
+		log("\n");
 		log("    -map {filename}\n");
 		log("        pass this option to techmap.\n");
 		log("\n");
@@ -545,7 +549,7 @@ struct TestCellPass : public Pass {
 	{
 		int num_iter = 100;
 		std::string techmap_cmd = "techmap -assert";
-		std::string ilang_file;
+		std::string ilang_file, write_prefix;
 		xorshift32_state = 0;
 		std::ofstream vlog_file;
 		bool verbose = false;
@@ -572,6 +576,10 @@ struct TestCellPass : public Pass {
 				num_iter = 1;
 				continue;
 			}
+			if (args[argidx] == "-w" && argidx+1 < GetSize(args)) {
+				write_prefix = args[++argidx];
+				continue;
+			}
 			if (args[argidx] == "-script" && argidx+1 < GetSize(args)) {
 				techmap_cmd = "script " + args[++argidx];
 				continue;
@@ -675,6 +683,15 @@ struct TestCellPass : public Pass {
 				continue;
 			}
 
+			if (args[argidx].substr(0, 1) == "/") {
+				std::vector<std::string> new_selected_cell_types;
+				for (auto it : selected_cell_types)
+					if (it != args[argidx].substr(1))
+						new_selected_cell_types.push_back(it);
+				new_selected_cell_types.swap(selected_cell_types);
+				continue;
+			}
+
 			if (cell_types.count(args[argidx]) == 0) {
 				std::string cell_type_list;
 				int charcount = 100;
@@ -713,23 +730,27 @@ struct TestCellPass : public Pass {
 					Frontend::frontend_call(design, NULL, std::string(), "ilang " + ilang_file);
 				else
 					create_gold_module(design, cell_type, cell_types.at(cell_type), constmode);
-				Pass::call(design, stringf("copy gold gate; cd gate; %s; cd ..; opt -fast gate", techmap_cmd.c_str()));
-				if (!nosat)
-					Pass::call(design, "miter -equiv -flatten -make_outputs -ignore_gold_x gold gate miter");
-				if (verbose)
-					Pass::call(design, "dump gate");
-				Pass::call(design, "dump gold");
-				if (!nosat)
-					Pass::call(design, "sat -verify -enable_undef -prove trigger 0 -show-inputs -show-outputs miter");
-				std::string uut_name = stringf("uut_%s_%d", cell_type.substr(1).c_str(), i);
-				if (vlog_file.is_open()) {
-					Pass::call(design, stringf("copy gold %s_expr; select %s_expr", uut_name.c_str(), uut_name.c_str()));
-					Backend::backend_call(design, &vlog_file, "<test_cell -vlog>", "verilog -selected");
-					Pass::call(design, stringf("copy gold %s_noexpr; select %s_noexpr", uut_name.c_str(), uut_name.c_str()));
-					Backend::backend_call(design, &vlog_file, "<test_cell -vlog>", "verilog -selected -noexpr");
-					uut_names.push_back(uut_name);
+				if (!write_prefix.empty()) {
+					Pass::call(design, stringf("write_ilang %s_%s_%05d.il", write_prefix.c_str(), cell_type.c_str()+1, i));
+				} else {
+					Pass::call(design, stringf("copy gold gate; cd gate; %s; cd ..; opt -fast gate", techmap_cmd.c_str()));
+					if (!nosat)
+						Pass::call(design, "miter -equiv -flatten -make_outputs -ignore_gold_x gold gate miter");
+					if (verbose)
+						Pass::call(design, "dump gate");
+					Pass::call(design, "dump gold");
+					if (!nosat)
+						Pass::call(design, "sat -verify -enable_undef -prove trigger 0 -show-inputs -show-outputs miter");
+					std::string uut_name = stringf("uut_%s_%d", cell_type.substr(1).c_str(), i);
+					if (vlog_file.is_open()) {
+						Pass::call(design, stringf("copy gold %s_expr; select %s_expr", uut_name.c_str(), uut_name.c_str()));
+						Backend::backend_call(design, &vlog_file, "<test_cell -vlog>", "verilog -selected");
+						Pass::call(design, stringf("copy gold %s_noexpr; select %s_noexpr", uut_name.c_str(), uut_name.c_str()));
+						Backend::backend_call(design, &vlog_file, "<test_cell -vlog>", "verilog -selected -noexpr");
+						uut_names.push_back(uut_name);
+					}
+					run_eval_test(design, verbose, nosat, uut_name, vlog_file);
 				}
-				run_eval_test(design, verbose, nosat, uut_name, vlog_file);
 				delete design;
 			}