Renamed SIZE() to GetSize() because of name collision on Win32

3 files changed, 44 insertions, 44 deletions

diff --git a/passes/tests/test_abcloop.cc b/passes/tests/test_abcloop.cc
index 1ede137ee..853339b95 100644
--- a/passes/tests/test_abcloop.cc
+++ b/passes/tests/test_abcloop.cc
@@ -36,7 +36,7 @@ static uint32_t xorshift32(uint32_t limit) {
 static RTLIL::Wire *getw(std::vector<RTLIL::Wire*> &wires, RTLIL::Wire *w)
 {
 	while (1) {
-		int idx = xorshift32(SIZE(wires));
+		int idx = xorshift32(GetSize(wires));
 		if (wires[idx] != w && !wires[idx]->port_output)
 			return wires[idx];
 	}
@@ -144,7 +144,7 @@ static void test_abcloop()
 		for (int i = 0; i < 16; i++)
 		{
 			std::vector<int> assumptions;
-			for (int j = 0; j < SIZE(in_vec); j++)
+			for (int j = 0; j < GetSize(in_vec); j++)
 				assumptions.push_back((i & (1 << j)) ? in_vec.at(j) : inverse_in_vec.at(j));
 
 			std::vector<bool> results;
@@ -197,7 +197,7 @@ static void test_abcloop()
 	for (int i = 0; i < 16; i++)
 	{
 		std::vector<int> assumptions;
-		for (int j = 0; j < SIZE(in_vec); j++)
+		for (int j = 0; j < GetSize(in_vec); j++)
 			assumptions.push_back((i & (1 << j)) ? in_vec.at(j) : inverse_in_vec.at(j));
 
 		for (int j = 0; j < 4; j++)
@@ -265,13 +265,13 @@ struct TestAbcloopPass : public Pass {
 		xorshift32_state = 0;
 
 		int argidx;
-		for (argidx = 1; argidx < SIZE(args); argidx++)
+		for (argidx = 1; argidx < GetSize(args); argidx++)
 		{
-			if (args[argidx] == "-n" && argidx+1 < SIZE(args)) {
+			if (args[argidx] == "-n" && argidx+1 < GetSize(args)) {
 				num_iter = atoi(args[++argidx].c_str());
 				continue;
 			}
-			if (args[argidx] == "-s" && argidx+1 < SIZE(args)) {
+			if (args[argidx] == "-s" && argidx+1 < GetSize(args)) {
 				xorshift32_state = atoi(args[++argidx].c_str());
 				continue;
 			}
diff --git a/passes/tests/test_autotb.cc b/passes/tests/test_autotb.cc
index 05caf6b21..9713ea061 100644
--- a/passes/tests/test_autotb.cc
+++ b/passes/tests/test_autotb.cc
@@ -336,9 +336,9 @@ struct TestAutotbBackend : public Backend {
 		log_header("Executing TEST_AUTOTB backend (auto-generate pseudo-random test benches).\n");
 
 		int argidx;
-		for (argidx = 1; argidx < SIZE(args); argidx++)
+		for (argidx = 1; argidx < GetSize(args); argidx++)
 		{
-			if (args[argidx] == "-n" && argidx+1 < SIZE(args)) {
+			if (args[argidx] == "-n" && argidx+1 < GetSize(args)) {
 				num_iter = atoi(args[++argidx].c_str());
 				continue;
 			}
diff --git a/passes/tests/test_cell.cc b/passes/tests/test_cell.cc
index d611d56c3..03fb31d28 100644
--- a/passes/tests/test_cell.cc
+++ b/passes/tests/test_cell.cc
@@ -213,12 +213,12 @@ static void create_gold_module(RTLIL::Design *design, RTLIL::IdString cell_type,
 		cell->setPort("\\BI", wire);
 
 		wire = module->addWire("\\X");
-		wire->width = SIZE(cell->getPort("\\Y"));
+		wire->width = GetSize(cell->getPort("\\Y"));
 		wire->port_output = true;
 		cell->setPort("\\X", wire);
 
 		wire = module->addWire("\\CO");
-		wire->width = SIZE(cell->getPort("\\Y"));
+		wire->width = GetSize(cell->getPort("\\Y"));
 		wire->port_output = true;
 		cell->setPort("\\CO", wire);
 	}
@@ -230,25 +230,25 @@ static void create_gold_module(RTLIL::Design *design, RTLIL::IdString cell_type,
 		{
 			RTLIL::SigSpec sig = conn.second;
 
-			if (SIZE(sig) == 0 || sig[0].wire == nullptr || sig[0].wire->port_output)
+			if (GetSize(sig) == 0 || sig[0].wire == nullptr || sig[0].wire->port_output)
 				continue;
 
 			int n, m;
 			switch (xorshift32(5))
 			{
 			case 0:
-				n = xorshift32(SIZE(sig) + 1);
+				n = xorshift32(GetSize(sig) + 1);
 				for (int i = 0; i < n; i++)
 					sig[i] = xorshift32(2) == 1 ? RTLIL::S1 : RTLIL::S0;
 				break;
 			case 1:
-				n = xorshift32(SIZE(sig) + 1);
-				for (int i = n; i < SIZE(sig); i++)
+				n = xorshift32(GetSize(sig) + 1);
+				for (int i = n; i < GetSize(sig); i++)
 					sig[i] = xorshift32(2) == 1 ? RTLIL::S1 : RTLIL::S0;
 				break;
 			case 2:
-				n = xorshift32(SIZE(sig));
-				m = xorshift32(SIZE(sig));
+				n = xorshift32(GetSize(sig));
+				m = xorshift32(GetSize(sig));
 				for (int i = std::min(n, m); i < std::max(n, m); i++)
 					sig[i] = xorshift32(2) == 1 ? RTLIL::S1 : RTLIL::S0;
 				break;
@@ -290,19 +290,19 @@ static void run_eval_test(RTLIL::Design *design, bool verbose, bool nosat, std::
 		for (auto port : gold_mod->ports) {
 			RTLIL::Wire *wire = gold_mod->wire(port);
 			if (wire->port_input)
-				vlog_file << stringf("  reg [%d:0] %s;\n", SIZE(wire)-1, log_id(wire));
+				vlog_file << stringf("  reg [%d:0] %s;\n", GetSize(wire)-1, log_id(wire));
 			else
-				vlog_file << stringf("  wire [%d:0] %s_expr, %s_noexpr;\n", SIZE(wire)-1, log_id(wire), log_id(wire));
+				vlog_file << stringf("  wire [%d:0] %s_expr, %s_noexpr;\n", GetSize(wire)-1, log_id(wire), log_id(wire));
 		}
 
 		vlog_file << stringf("  %s_expr uut_expr(", uut_name.c_str());
-		for (int i = 0; i < SIZE(gold_mod->ports); i++)
+		for (int i = 0; i < GetSize(gold_mod->ports); i++)
 			vlog_file << stringf("%s.%s(%s%s)", i ? ", " : "", log_id(gold_mod->ports[i]), log_id(gold_mod->ports[i]),
 					gold_mod->wire(gold_mod->ports[i])->port_input ? "" : "_expr");
 		vlog_file << stringf(");\n");
 
 		vlog_file << stringf("  %s_expr uut_noexpr(", uut_name.c_str());
-		for (int i = 0; i < SIZE(gold_mod->ports); i++)
+		for (int i = 0; i < GetSize(gold_mod->ports); i++)
 			vlog_file << stringf("%s.%s(%s%s)", i ? ", " : "", log_id(gold_mod->ports[i]), log_id(gold_mod->ports[i]),
 					gold_mod->wire(gold_mod->ports[i])->port_input ? "" : "_noexpr");
 		vlog_file << stringf(");\n");
@@ -330,18 +330,18 @@ static void run_eval_test(RTLIL::Design *design, bool verbose, bool nosat, std::
 			log_assert(gold_wire != nullptr);
 			log_assert(gate_wire != nullptr);
 			log_assert(gold_wire->port_input == gate_wire->port_input);
-			log_assert(SIZE(gold_wire) == SIZE(gate_wire));
+			log_assert(GetSize(gold_wire) == GetSize(gate_wire));
 
 			if (!gold_wire->port_input)
 				continue;
 
 			RTLIL::Const in_value;
-			for (int i = 0; i < SIZE(gold_wire); i++)
+			for (int i = 0; i < GetSize(gold_wire); i++)
 				in_value.bits.push_back(xorshift32(2) ? RTLIL::S1 : RTLIL::S0);
 
 			if (xorshift32(4) == 0) {
 				int inv_chance = 1 + xorshift32(8);
-				for (int i = 0; i < SIZE(gold_wire); i++)
+				for (int i = 0; i < GetSize(gold_wire); i++)
 					if (xorshift32(inv_chance) == 0)
 						in_value.bits[i] = RTLIL::Sx;
 			}
@@ -355,7 +355,7 @@ static void run_eval_test(RTLIL::Design *design, bool verbose, bool nosat, std::
 			gold_ce.set(gold_wire, in_value);
 			gate_ce.set(gate_wire, in_value);
 
-			if (vlog_file.is_open() && SIZE(in_value) > 0) {
+			if (vlog_file.is_open() && GetSize(in_value) > 0) {
 				vlog_file << stringf("      %s = 'b%s;\n", log_id(gold_wire), in_value.as_string().c_str());
 				if (!vlog_pattern_info.empty())
 					vlog_pattern_info += " ";
@@ -374,7 +374,7 @@ static void run_eval_test(RTLIL::Design *design, bool verbose, bool nosat, std::
 			log_assert(gold_wire != nullptr);
 			log_assert(gate_wire != nullptr);
 			log_assert(gold_wire->port_output == gate_wire->port_output);
-			log_assert(SIZE(gold_wire) == SIZE(gate_wire));
+			log_assert(GetSize(gold_wire) == GetSize(gate_wire));
 
 			if (!gold_wire->port_output)
 				continue;
@@ -389,7 +389,7 @@ static void run_eval_test(RTLIL::Design *design, bool verbose, bool nosat, std::
 				log_error("Failed to eval %s in gate module.\n", log_id(gate_wire));
 
 			bool gold_gate_mismatch = false;
-			for (int i = 0; i < SIZE(gold_wire); i++) {
+			for (int i = 0; i < GetSize(gold_wire); i++) {
 				if (gold_outval[i] == RTLIL::Sx)
 					continue;
 				if (gold_outval[i] == gate_outval[i])
@@ -409,9 +409,9 @@ static void run_eval_test(RTLIL::Design *design, bool verbose, bool nosat, std::
 
 			if (vlog_file.is_open()) {
 				vlog_file << stringf("      $display(\"[%s] %s expected: %%b, expr: %%b, noexpr: %%b\", %d'b%s, %s_expr, %s_noexpr);\n",
-						vlog_pattern_info.c_str(), log_id(gold_wire), SIZE(gold_outval), gold_outval.as_string().c_str(), log_id(gold_wire), log_id(gold_wire));
-				vlog_file << stringf("      if (%s_expr !== %d'b%s) begin $display(\"ERROR\"); $finish; end\n", log_id(gold_wire), SIZE(gold_outval), gold_outval.as_string().c_str());
-				vlog_file << stringf("      if (%s_noexpr !== %d'b%s) begin $display(\"ERROR\"); $finish; end\n", log_id(gold_wire), SIZE(gold_outval), gold_outval.as_string().c_str());
+						vlog_pattern_info.c_str(), log_id(gold_wire), GetSize(gold_outval), gold_outval.as_string().c_str(), log_id(gold_wire), log_id(gold_wire));
+				vlog_file << stringf("      if (%s_expr !== %d'b%s) begin $display(\"ERROR\"); $finish; end\n", log_id(gold_wire), GetSize(gold_outval), gold_outval.as_string().c_str());
+				vlog_file << stringf("      if (%s_noexpr !== %d'b%s) begin $display(\"ERROR\"); $finish; end\n", log_id(gold_wire), GetSize(gold_outval), gold_outval.as_string().c_str());
 			}
 		}
 
@@ -431,12 +431,12 @@ static void run_eval_test(RTLIL::Design *design, bool verbose, bool nosat, std::
 
 			if (verbose) {
 				log("SAT 1: ");
-				for (int i = SIZE(out_sig)-1; i >= 0; i--)
+				for (int i = GetSize(out_sig)-1; i >= 0; i--)
 					log("%c", sat1_model_value.at(i) ? '1' : '0');
 				log("\n");
 			}
 
-			for (int i = 0; i < SIZE(out_sig); i++) {
+			for (int i = 0; i < GetSize(out_sig); i++) {
 				if (out_val[i] != RTLIL::S0 && out_val[i] != RTLIL::S1)
 					continue;
 				if (out_val[i] == RTLIL::S0 && sat1_model_value.at(i) == false)
@@ -466,13 +466,13 @@ static void run_eval_test(RTLIL::Design *design, bool verbose, bool nosat, std::
 
 			if (verbose) {
 				log("SAT 2: ");
-				for (int i = SIZE(out_sig)-1; i >= 0; i--)
-					log("%c", sat2_model_value.at(SIZE(out_sig) + i) ? 'x' : sat2_model_value.at(i) ? '1' : '0');
+				for (int i = GetSize(out_sig)-1; i >= 0; i--)
+					log("%c", sat2_model_value.at(GetSize(out_sig) + i) ? 'x' : sat2_model_value.at(i) ? '1' : '0');
 				log("\n");
 			}
 
-			for (int i = 0; i < SIZE(out_sig); i++) {
-				if (sat2_model_value.at(SIZE(out_sig) + i)) {
+			for (int i = 0; i < GetSize(out_sig); i++) {
+				if (sat2_model_value.at(GetSize(out_sig) + i)) {
 					if (out_val[i] != RTLIL::S0 && out_val[i] != RTLIL::S1)
 						continue;
 				} else {
@@ -553,26 +553,26 @@ struct TestCellPass : public Pass {
 		bool nosat = false;
 
 		int argidx;
-		for (argidx = 1; argidx < SIZE(args); argidx++)
+		for (argidx = 1; argidx < GetSize(args); argidx++)
 		{
-			if (args[argidx] == "-n" && argidx+1 < SIZE(args)) {
+			if (args[argidx] == "-n" && argidx+1 < GetSize(args)) {
 				num_iter = atoi(args[++argidx].c_str());
 				continue;
 			}
-			if (args[argidx] == "-s" && argidx+1 < SIZE(args)) {
+			if (args[argidx] == "-s" && argidx+1 < GetSize(args)) {
 				xorshift32_state = atoi(args[++argidx].c_str());
 				continue;
 			}
-			if (args[argidx] == "-map" && argidx+1 < SIZE(args)) {
+			if (args[argidx] == "-map" && argidx+1 < GetSize(args)) {
 				techmap_cmd += " -map " + args[++argidx];
 				continue;
 			}
-			if (args[argidx] == "-f" && argidx+1 < SIZE(args)) {
+			if (args[argidx] == "-f" && argidx+1 < GetSize(args)) {
 				ilang_file = args[++argidx];
 				num_iter = 1;
 				continue;
 			}
-			if (args[argidx] == "-script" && argidx+1 < SIZE(args)) {
+			if (args[argidx] == "-script" && argidx+1 < GetSize(args)) {
 				techmap_cmd = "script " + args[++argidx];
 				continue;
 			}
@@ -592,7 +592,7 @@ struct TestCellPass : public Pass {
 				verbose = true;
 				continue;
 			}
-			if (args[argidx] == "-vlog" && argidx+1 < SIZE(args)) {
+			if (args[argidx] == "-vlog" && argidx+1 < GetSize(args)) {
 				vlog_file.open(args[++argidx], std::ios_base::trunc);
 				if (!vlog_file.is_open())
 					log_cmd_error("Failed to open output file `%s'.\n", args[argidx].c_str());
@@ -663,7 +663,7 @@ struct TestCellPass : public Pass {
 		cell_types["$macc"] = "*";
 		cell_types["$fa"] = "*";
 
-		for (; argidx < SIZE(args); argidx++)
+		for (; argidx < GetSize(args); argidx++)
 		{
 			if (args[argidx].rfind("-", 0) == 0)
 				log_cmd_error("Unexpected option: %s\n", args[argidx].c_str());
@@ -684,7 +684,7 @@ struct TestCellPass : public Pass {
 						charcount = 0;
 					} else
 						cell_type_list += " " + it.first;
-					charcount += SIZE(it.first);
+					charcount += GetSize(it.first);
 				}
 				log_cmd_error("The cell type `%s' is currently not supported. Try one of these:%s\n",
 						args[argidx].c_str(), cell_type_list.c_str());