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| author | Clifford Wolf <clifford@clifford.at> | 2014-10-18 16:52:06 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-10-18 16:52:06 +0100 |
| commit | 41db98ba3113b45220ad5300c51e608f89c1d263 (patch) | |
| tree | 1fc1ea3277cf561d3e3fab7a310573fe41fb371a /passes/tests | |
| parent | 6bcb4f1f45d1310718d356b7e439bd87fc7d045a (diff) | |
| download | yosys-41db98ba3113b45220ad5300c51e608f89c1d263.tar.gz yosys-41db98ba3113b45220ad5300c51e608f89c1d263.tar.bz2 yosys-41db98ba3113b45220ad5300c51e608f89c1d263.zip | |
Fixed typo in test_cell
Diffstat (limited to 'passes/tests')
| -rw-r--r-- | passes/tests/test_cell.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/tests/test_cell.cc b/passes/tests/test_cell.cc index 03fb31d28..3406d7e3e 100644 --- a/passes/tests/test_cell.cc +++ b/passes/tests/test_cell.cc @@ -522,7 +522,7 @@ struct TestCellPass : public Pass { log(" -map {filename}\n"); log(" pass this option to techmap.\n"); log("\n"); - log(" -simplib\n"); + log(" -simlib\n"); log(" use \"techmap -map +/simlib.v -max_iter 2 -autoproc\"\n"); log("\n"); log(" -script {script_file}\n"); |