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| author | whitequark <whitequark@whitequark.org> | 2020-06-19 06:15:33 +0000 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-06-19 06:15:33 +0000 |
| commit | ede4b10da8fdbdcff900b93c6c723516901483ff (patch) | |
| tree | d949c995f56d6c07dfe7d18ca46547a3296079b6 /passes/tests/test_cell.cc | |
| parent | bcbd44c673e07c44da735ef1d7f6eb2b6c328f98 (diff) | |
| parent | 60478a8e3a7b929ea7e4f4cd1b538b41ca1f34bb (diff) | |
| download | yosys-ede4b10da8fdbdcff900b93c6c723516901483ff.tar.gz yosys-ede4b10da8fdbdcff900b93c6c723516901483ff.tar.bz2 yosys-ede4b10da8fdbdcff900b93c6c723516901483ff.zip | |
Merge pull request #2173 from whitequark/use-cxx11-final-override
Use C++11 final/override/[[noreturn]]
Diffstat (limited to 'passes/tests/test_cell.cc')
| -rw-r--r-- | passes/tests/test_cell.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/passes/tests/test_cell.cc b/passes/tests/test_cell.cc index c6801007d..942468e29 100644 --- a/passes/tests/test_cell.cc +++ b/passes/tests/test_cell.cc @@ -652,7 +652,7 @@ static void run_eval_test(RTLIL::Design *design, bool verbose, bool nosat, std:: struct TestCellPass : public Pass { TestCellPass() : Pass("test_cell", "automatically test the implementation of a cell type") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -712,7 +712,7 @@ struct TestCellPass : public Pass { log(" create a Verilog test bench to test simlib and write_verilog\n"); log("\n"); } - void execute(std::vector<std::string> args, RTLIL::Design*) YS_OVERRIDE + void execute(std::vector<std::string> args, RTLIL::Design*) override { int num_iter = 100; std::string techmap_cmd = "techmap -assert"; |