diff options
| author | Clifford Wolf <clifford@clifford.at> | 2013-10-24 11:37:54 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2013-10-24 11:37:54 +0200 |
| commit | e679a5d04633e0c0626057ed2760ddb9595eea5d (patch) | |
| tree | cce75cbef78ff294cc26a992347fe16b713db996 /passes/techmap | |
| parent | e9dede01ca8834ea3c211862a5d6c0119b2b578a (diff) | |
| download | yosys-e679a5d04633e0c0626057ed2760ddb9595eea5d.tar.gz yosys-e679a5d04633e0c0626057ed2760ddb9595eea5d.tar.bz2 yosys-e679a5d04633e0c0626057ed2760ddb9595eea5d.zip | |
Fixed handling of boolean attributes (passes)
Diffstat (limited to 'passes/techmap')
| -rw-r--r-- | passes/techmap/iopadmap.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/techmap/iopadmap.cc b/passes/techmap/iopadmap.cc index 03d0d181c..134211e5f 100644 --- a/passes/techmap/iopadmap.cc +++ b/passes/techmap/iopadmap.cc @@ -144,7 +144,7 @@ struct IopadmapPass : public Pass { cell->parameters[RTLIL::escape_id(widthparam)] = RTLIL::Const(wire->width); if (!nameparam.empty()) cell->parameters[RTLIL::escape_id(nameparam)] = RTLIL::Const(RTLIL::id2cstr(wire->name)); - cell->attributes["\\keep"] = RTLIL::Const(); + cell->attributes["\\keep"] = RTLIL::Const(1); module->add(cell); wire->port_id = 0; |