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| author | Clifford Wolf <clifford@clifford.at> | 2016-05-07 09:33:16 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2016-05-07 09:33:16 +0200 |
| commit | c3f6e0ea851b90b11671015f2bb472c857f0e2d9 (patch) | |
| tree | ac94967a1dfb2798902638dd4312ae299dc2551a /passes/techmap | |
| parent | 6fe3d5a1cf938081110db0470def2b2687dd665f (diff) | |
| download | yosys-c3f6e0ea851b90b11671015f2bb472c857f0e2d9.tar.gz yosys-c3f6e0ea851b90b11671015f2bb472c857f0e2d9.tar.bz2 yosys-c3f6e0ea851b90b11671015f2bb472c857f0e2d9.zip | |
Added support for "keep" attribute to shregmap
Diffstat (limited to 'passes/techmap')
| -rw-r--r-- | passes/techmap/shregmap.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/passes/techmap/shregmap.cc b/passes/techmap/shregmap.cc index 766c1c65f..6936b499e 100644 --- a/passes/techmap/shregmap.cc +++ b/passes/techmap/shregmap.cc @@ -112,7 +112,7 @@ struct ShregmapWorker { for (auto wire : module->wires()) { - if (wire->port_output) { + if (wire->port_output || wire->get_bool_attribute("\\keep")) { for (auto bit : sigmap(wire)) sigbit_with_non_chain_users.insert(bit); } @@ -130,7 +130,7 @@ struct ShregmapWorker for (auto cell : module->cells()) { - if (opts.ffcells.count(cell->type)) + if (opts.ffcells.count(cell->type) && !cell->get_bool_attribute("\\keep")) { IdString d_port = opts.ffcells.at(cell->type).first; IdString q_port = opts.ffcells.at(cell->type).second; |