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| author | Clifford Wolf <clifford@clifford.at> | 2013-12-21 20:47:22 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2013-12-21 20:47:22 +0100 |
| commit | 334b0cc8033490de29b4ac896d0dcc2ecab0e59b (patch) | |
| tree | 195cdad7d50f5606396c748fc0c5ca4d42162070 /passes/techmap | |
| parent | 8856cec308932d224da2061ca59d0eacf90f4793 (diff) | |
| download | yosys-334b0cc8033490de29b4ac896d0dcc2ecab0e59b.tar.gz yosys-334b0cc8033490de29b4ac896d0dcc2ecab0e59b.tar.bz2 yosys-334b0cc8033490de29b4ac896d0dcc2ecab0e59b.zip | |
Fixed dfflibmap for unused output ports
Diffstat (limited to 'passes/techmap')
| -rw-r--r-- | passes/techmap/dfflibmap.cc | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/passes/techmap/dfflibmap.cc b/passes/techmap/dfflibmap.cc index 6fbd52105..40caf7801 100644 --- a/passes/techmap/dfflibmap.cc +++ b/passes/techmap/dfflibmap.cc @@ -419,6 +419,7 @@ static void dfflibmap(RTLIL::Design *design, RTLIL::Module *module) if (port.second == '0' || port.second == '1') { sig = RTLIL::SigSpec(port.second == '0' ? 0 : 1, 1); } else + if (port.second != 0) log_abort(); new_cell->connections["\\" + port.first] = sig; } |