diff options
| author | Kristoffer Ellersgaard Koch <kristoffer.koch@gmail.com> | 2019-05-05 10:00:27 +0200 |
|---|---|---|
| committer | Kristoffer Ellersgaard Koch <kristoffer.koch@gmail.com> | 2019-05-08 10:27:14 +0200 |
| commit | 30c762d3a148afa9e27a93c1fa098b7c478511a4 (patch) | |
| tree | b27299c6f35a630a9b1df53d8721850d87ee7b3d /passes/techmap | |
| parent | a01386c0e45b4eee5295db440740a1ab271396fe (diff) | |
| download | yosys-30c762d3a148afa9e27a93c1fa098b7c478511a4.tar.gz yosys-30c762d3a148afa9e27a93c1fa098b7c478511a4.tar.bz2 yosys-30c762d3a148afa9e27a93c1fa098b7c478511a4.zip | |
Fix all warnings that occurred when compiling with gcc9
Diffstat (limited to 'passes/techmap')
| -rw-r--r-- | passes/techmap/flowmap.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/passes/techmap/flowmap.cc b/passes/techmap/flowmap.cc index 0b7931e48..f5892a60e 100644 --- a/passes/techmap/flowmap.cc +++ b/passes/techmap/flowmap.cc @@ -397,7 +397,6 @@ struct FlowGraph pool<RTLIL::SigBit> x, xi; NodePrime source_prime = {source, true}; - NodePrime sink_prime = {sink, false}; pool<NodePrime> visited; vector<NodePrime> worklist = {source_prime}; while (!worklist.empty()) @@ -1382,7 +1381,8 @@ struct FlowmapWorker vector<RTLIL::SigBit> input_nodes(lut_edges_bw[node].begin(), lut_edges_bw[node].end()); RTLIL::Const lut_table(State::Sx, max(1 << input_nodes.size(), 1 << minlut)); - for (unsigned i = 0; i < (1 << input_nodes.size()); i++) + unsigned const mask = 1 << input_nodes.size(); + for (unsigned i = 0; i < mask; i++) { ce.push(); for (size_t n = 0; n < input_nodes.size(); n++) |