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| author | Clifford Wolf <clifford@clifford.at> | 2015-06-10 23:00:12 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2015-06-10 23:00:12 +0200 |
| commit | 1ae360cf725db65c54c69042bcef66f1728b4df6 (patch) | |
| tree | 5dca46356d177859372621dd31c02075221a80f9 /passes/techmap | |
| parent | e5348817947be85cb69f42c7e0ec0706d0511f0f (diff) | |
| download | yosys-1ae360cf725db65c54c69042bcef66f1728b4df6.tar.gz yosys-1ae360cf725db65c54c69042bcef66f1728b4df6.tar.bz2 yosys-1ae360cf725db65c54c69042bcef66f1728b4df6.zip | |
AigMaker refactoring
Diffstat (limited to 'passes/techmap')
| -rw-r--r-- | passes/techmap/aigmap.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/techmap/aigmap.cc b/passes/techmap/aigmap.cc index 9f552e3e5..5253b0f8a 100644 --- a/passes/techmap/aigmap.cc +++ b/passes/techmap/aigmap.cc @@ -89,7 +89,7 @@ struct AigmapPass : public Pass { if (node.portbit >= 0) { bit = cell->getPort(node.portname)[node.portbit]; } else if (node.left_parent < 0 && node.right_parent < 0) { - bit = node.inverter ? State::S0 : State::S1; + bit = node.inverter ? State::S1 : State::S0; goto skip_inverter; } else { SigBit A = sigs.at(node.left_parent); |