diff options
| author | Clifford Wolf <clifford@clifford.at> | 2019-04-18 17:42:12 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2019-04-18 17:45:47 +0200 |
| commit | f4abc21d8ad79621cc24852bd76abf40a9d9f702 (patch) | |
| tree | 016692552e9880b3e37a715b53f45db707c83a91 /passes/techmap/techmap.cc | |
| parent | ea8ac0aaad3a1f89ead8eb44b2fef5927f29a099 (diff) | |
| download | yosys-f4abc21d8ad79621cc24852bd76abf40a9d9f702.tar.gz yosys-f4abc21d8ad79621cc24852bd76abf40a9d9f702.tar.bz2 yosys-f4abc21d8ad79621cc24852bd76abf40a9d9f702.zip | |
Add "whitebox" attribute, add "read_verilog -wb"
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Diffstat (limited to 'passes/techmap/techmap.cc')
| -rw-r--r-- | passes/techmap/techmap.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc index d0e5e2236..d694e8165 100644 --- a/passes/techmap/techmap.cc +++ b/passes/techmap/techmap.cc @@ -472,7 +472,7 @@ struct TechmapWorker RTLIL::Module *tpl = map->modules_[tpl_name]; std::map<RTLIL::IdString, RTLIL::Const> parameters(cell->parameters.begin(), cell->parameters.end()); - if (tpl->get_bool_attribute("\\blackbox")) + if (tpl->get_blackbox_attribute()) continue; if (!flatten_mode) @@ -1209,7 +1209,7 @@ struct FlattenPass : public Pass { dict<RTLIL::IdString, RTLIL::Module*> new_modules; for (auto mod : vector<Module*>(design->modules())) - if (used_modules[mod->name] || mod->get_bool_attribute("\\blackbox")) { + if (used_modules[mod->name] || mod->get_blackbox_attribute()) { new_modules[mod->name] = mod; } else { log("Deleting now unused module %s.\n", log_id(mod)); |