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| author | Jannis Harder <me@jix.one> | 2023-01-11 16:26:04 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2023-01-11 16:26:04 +0100 |
| commit | 5abaa5908082f13f6b574d66f6f8a9ebb476fd54 (patch) | |
| tree | 4438609065528688666e63ffa2e737bced73d35c /passes/techmap/simplemap.h | |
| parent | d742d063d4e887f3e4dba8bab1a37d160596977d (diff) | |
| parent | eb0039848b42afa196f440301492a5afc09b4cf4 (diff) | |
| download | yosys-5abaa5908082f13f6b574d66f6f8a9ebb476fd54.tar.gz yosys-5abaa5908082f13f6b574d66f6f8a9ebb476fd54.tar.bz2 yosys-5abaa5908082f13f6b574d66f6f8a9ebb476fd54.zip | |
Merge pull request #3537 from jix/xprop
New xprop pass
Diffstat (limited to 'passes/techmap/simplemap.h')
| -rw-r--r-- | passes/techmap/simplemap.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/passes/techmap/simplemap.h b/passes/techmap/simplemap.h index c7654f68c..30cc1ccfe 100644 --- a/passes/techmap/simplemap.h +++ b/passes/techmap/simplemap.h @@ -31,6 +31,7 @@ extern void simplemap_reduce(RTLIL::Module *module, RTLIL::Cell *cell); extern void simplemap_lognot(RTLIL::Module *module, RTLIL::Cell *cell); extern void simplemap_logbin(RTLIL::Module *module, RTLIL::Cell *cell); extern void simplemap_mux(RTLIL::Module *module, RTLIL::Cell *cell); +extern void simplemap_bwmux(RTLIL::Module *module, RTLIL::Cell *cell); extern void simplemap_lut(RTLIL::Module *module, RTLIL::Cell *cell); extern void simplemap_slice(RTLIL::Module *module, RTLIL::Cell *cell); extern void simplemap_concat(RTLIL::Module *module, RTLIL::Cell *cell); |