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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-15 14:51:12 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-15 14:51:12 -0700 |
| commit | eae5a6b12c0f44230f61ed23068e7200507f9520 (patch) | |
| tree | 51fffae9b283c2310acf18b80ec814f2602ac342 /passes/techmap/shregmap.cc | |
| parent | 52355f5185fe42e28775e897f458b38a439c0ec5 (diff) | |
| download | yosys-eae5a6b12c0f44230f61ed23068e7200507f9520.tar.gz yosys-eae5a6b12c0f44230f61ed23068e7200507f9520.tar.bz2 yosys-eae5a6b12c0f44230f61ed23068e7200507f9520.zip | |
Use ID::keep more liberally too
Diffstat (limited to 'passes/techmap/shregmap.cc')
| -rw-r--r-- | passes/techmap/shregmap.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/passes/techmap/shregmap.cc b/passes/techmap/shregmap.cc index cb877c2f4..5e298d8dd 100644 --- a/passes/techmap/shregmap.cc +++ b/passes/techmap/shregmap.cc @@ -263,7 +263,7 @@ struct ShregmapWorker { for (auto wire : module->wires()) { - if (wire->port_output || wire->get_bool_attribute(ID(keep))) { + if (wire->port_output || wire->get_bool_attribute(ID::keep)) { for (auto bit : sigmap(wire)) { sigbit_with_non_chain_users.insert(bit); if (opts.tech) opts.tech->non_chain_user(bit, nullptr, {}); @@ -283,7 +283,7 @@ struct ShregmapWorker for (auto cell : module->cells()) { - if (opts.ffcells.count(cell->type) && !cell->get_bool_attribute(ID(keep))) + if (opts.ffcells.count(cell->type) && !cell->get_bool_attribute(ID::keep)) { IdString d_port = opts.ffcells.at(cell->type).first; IdString q_port = opts.ffcells.at(cell->type).second; |