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| author | Clifford Wolf <clifford@clifford.at> | 2019-05-06 15:41:13 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2019-05-06 15:41:13 +0200 |
| commit | d187be39d608966f53d6c2ba4d45de94a584d476 (patch) | |
| tree | 30b9820eddba4341c7270d5b255758967ed7eaf0 /passes/techmap/shregmap.cc | |
| parent | 5c2c0b4bb2ade51396da3acbcce0d5916fb1c7d6 (diff) | |
| parent | 20268d12a51e157effc209de5613f0ac8308a61f (diff) | |
| download | yosys-d187be39d608966f53d6c2ba4d45de94a584d476.tar.gz yosys-d187be39d608966f53d6c2ba4d45de94a584d476.tar.bz2 yosys-d187be39d608966f53d6c2ba4d45de94a584d476.zip | |
Merge branch 'master' of github.com:YosysHQ/yosys into clifford/fix968
Diffstat (limited to 'passes/techmap/shregmap.cc')
| -rw-r--r-- | passes/techmap/shregmap.cc | 12 |
1 files changed, 11 insertions, 1 deletions
diff --git a/passes/techmap/shregmap.cc b/passes/techmap/shregmap.cc index a541b33be..75eedfbcc 100644 --- a/passes/techmap/shregmap.cc +++ b/passes/techmap/shregmap.cc @@ -178,7 +178,17 @@ struct ShregmapTechXilinx7 : ShregmapTech // Only map if $shiftx exclusively covers the shift register if (shiftx->type == "$shiftx") { - if (GetSize(taps) != shiftx->getParam("\\A_WIDTH").as_int()) + if (GetSize(taps) > shiftx->getParam("\\A_WIDTH").as_int()) + return false; + // Due to padding the most significant bits of A may be 1'bx, + // and if so, discount them + if (GetSize(taps) < shiftx->getParam("\\A_WIDTH").as_int()) { + const SigSpec A = shiftx->getPort("\\A"); + const int A_width = shiftx->getParam("\\A_WIDTH").as_int(); + for (int i = GetSize(taps); i < A_width; ++i) + if (A[i] != RTLIL::Sx) return false; + } + else if (GetSize(taps) != shiftx->getParam("\\A_WIDTH").as_int()) return false; } else if (shiftx->type == "$mux") { |