diff options
| author | Eddie Hung <eddie@fpgeh.com> | 2019-06-21 11:17:19 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-21 11:17:19 -0700 |
| commit | 63eb5cace980cd34e59065e577c04abaad239ddf (patch) | |
| tree | be065a052bda42a4654e4a1483f9fcde0beacef9 /passes/techmap/shregmap.cc | |
| parent | 776d7cea6ad42a58f47cdcb7a71a801e1ea1055f (diff) | |
| parent | c4ea6fff65d6b2e69a31649af7e10b129c6ae0f5 (diff) | |
| download | yosys-63eb5cace980cd34e59065e577c04abaad239ddf.tar.gz yosys-63eb5cace980cd34e59065e577c04abaad239ddf.tar.bz2 yosys-63eb5cace980cd34e59065e577c04abaad239ddf.zip | |
Merge branch 'master' into eddie/muxpack
Diffstat (limited to 'passes/techmap/shregmap.cc')
| -rw-r--r-- | passes/techmap/shregmap.cc | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/passes/techmap/shregmap.cc b/passes/techmap/shregmap.cc index 21dfe9619..18e60fa6b 100644 --- a/passes/techmap/shregmap.cc +++ b/passes/techmap/shregmap.cc @@ -605,9 +605,11 @@ struct ShregmapPass : public Pass { log("\n"); log(" -tech greenpak4\n"); log(" map to greenpak4 shift registers.\n"); + log(" this option also implies -clkpol pos -zinit\n"); log("\n"); log(" -tech xilinx\n"); log(" map to xilinx dynamic-length shift registers.\n"); + log(" this option also implies -params -init\n"); log("\n"); } void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE |