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| author | Eddie Hung <eddie@fpgeh.com> | 2019-06-21 17:43:29 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-21 17:43:29 -0700 |
| commit | 1abe93e48d8bb78cd0753d46dfbe1885a1e803eb (patch) | |
| tree | ecaa95a9e3b9c87a528a6939a36053012cbea563 /passes/techmap/shregmap.cc | |
| parent | 0f300e75c07dbcf21ab2d6128ef8af9ca6a98892 (diff) | |
| parent | e01bab6c6437f7e3072e10beaec558d3f71c3e9e (diff) | |
| download | yosys-1abe93e48d8bb78cd0753d46dfbe1885a1e803eb.tar.gz yosys-1abe93e48d8bb78cd0753d46dfbe1885a1e803eb.tar.bz2 yosys-1abe93e48d8bb78cd0753d46dfbe1885a1e803eb.zip | |
Merge remote-tracking branch 'origin/master' into xaig
Diffstat (limited to 'passes/techmap/shregmap.cc')
| -rw-r--r-- | passes/techmap/shregmap.cc | 18 |
1 files changed, 15 insertions, 3 deletions
diff --git a/passes/techmap/shregmap.cc b/passes/techmap/shregmap.cc index 18e60fa6b..004ab1eb9 100644 --- a/passes/techmap/shregmap.cc +++ b/passes/techmap/shregmap.cc @@ -293,10 +293,22 @@ struct ShregmapWorker if (opts.init || sigbit_init.count(q_bit) == 0) { - if (sigbit_chain_next.count(d_bit)) { + auto r = sigbit_chain_next.insert(std::make_pair(d_bit, cell)); + if (!r.second) { + // Insertion not successful means that d_bit is already + // connected to another register, thus mark it as a + // non chain user ... sigbit_with_non_chain_users.insert(d_bit); - } else - sigbit_chain_next[d_bit] = cell; + // ... and clone d_bit into another wire, and use that + // wire as a different key in the d_bit-to-cell dictionary + // so that it can be identified as another chain + // (omitting this common flop) + // Link: https://github.com/YosysHQ/yosys/pull/1085 + Wire *wire = module->addWire(NEW_ID); + module->connect(wire, d_bit); + sigmap.add(wire, d_bit); + sigbit_chain_next.insert(std::make_pair(wire, cell)); + } sigbit_chain_prev[q_bit] = cell; continue; |