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authorSahand Kashani <sahand.kashani@gmail.com>2020-04-08 23:50:37 +0200
committerSahand Kashani <sahand.kashani@gmail.com>2020-04-08 23:50:37 +0200
commit9edf8869c18951ec2b75f074065f073da3253244 (patch)
tree09fba95ba6d3f93ecab828c84b9ff3f74160d7b9 /passes/techmap/lut2mux.cc
parent820e3d1dad4f484f9646588f79b73b21b495e3d8 (diff)
parent5f649fc19d5cef76a634572ad0a493f1d2fd6306 (diff)
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Merge branch 'master' of github.com:YosysHQ/yosys into firrtl_backend_fileinfo
Diffstat (limited to 'passes/techmap/lut2mux.cc')
-rw-r--r--passes/techmap/lut2mux.cc2
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/techmap/lut2mux.cc b/passes/techmap/lut2mux.cc
index c6618fc9d..703bf6ff6 100644
--- a/passes/techmap/lut2mux.cc
+++ b/passes/techmap/lut2mux.cc
@@ -27,7 +27,7 @@ int lut2mux(Cell *cell)
{
SigSpec sig_a = cell->getPort(ID::A);
SigSpec sig_y = cell->getPort(ID::Y);
- Const lut = cell->getParam(ID(LUT));
+ Const lut = cell->getParam(ID::LUT);
int count = 1;
if (GetSize(sig_a) == 1)