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| author | Sahand Kashani <sahand.kashani@gmail.com> | 2020-04-08 23:50:37 +0200 |
|---|---|---|
| committer | Sahand Kashani <sahand.kashani@gmail.com> | 2020-04-08 23:50:37 +0200 |
| commit | 9edf8869c18951ec2b75f074065f073da3253244 (patch) | |
| tree | 09fba95ba6d3f93ecab828c84b9ff3f74160d7b9 /passes/techmap/insbuf.cc | |
| parent | 820e3d1dad4f484f9646588f79b73b21b495e3d8 (diff) | |
| parent | 5f649fc19d5cef76a634572ad0a493f1d2fd6306 (diff) | |
| download | yosys-9edf8869c18951ec2b75f074065f073da3253244.tar.gz yosys-9edf8869c18951ec2b75f074065f073da3253244.tar.bz2 yosys-9edf8869c18951ec2b75f074065f073da3253244.zip | |
Merge branch 'master' of github.com:YosysHQ/yosys into firrtl_backend_fileinfo
Diffstat (limited to 'passes/techmap/insbuf.cc')
| -rw-r--r-- | passes/techmap/insbuf.cc | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/passes/techmap/insbuf.cc b/passes/techmap/insbuf.cc index 2173049b4..0686c0f2b 100644 --- a/passes/techmap/insbuf.cc +++ b/passes/techmap/insbuf.cc @@ -41,16 +41,16 @@ struct InsbufPass : public Pass { { log_header(design, "Executing INSBUF pass (insert buffer cells for connected wires).\n"); - std::string celltype = "$_BUF_", in_portname = "\\A", out_portname = "\\Y"; + IdString celltype = ID($_BUF_), in_portname = ID::A, out_portname = ID::Y; size_t argidx; for (argidx = 1; argidx < args.size(); argidx++) { std::string arg = args[argidx]; if (arg == "-buf" && argidx+3 < args.size()) { - celltype = args[++argidx]; - in_portname = args[++argidx]; - out_portname = args[++argidx]; + celltype = RTLIL::escape_id(args[++argidx]); + in_portname = RTLIL::escape_id(args[++argidx]); + out_portname = RTLIL::escape_id(args[++argidx]); continue; } break; @@ -76,9 +76,9 @@ struct InsbufPass : public Pass { continue; } - Cell *cell = module->addCell(NEW_ID, RTLIL::escape_id(celltype)); - cell->setPort(RTLIL::escape_id(in_portname), rhs); - cell->setPort(RTLIL::escape_id(out_portname), lhs); + Cell *cell = module->addCell(NEW_ID, celltype); + cell->setPort(in_portname, rhs); + cell->setPort(out_portname, lhs); log("Added %s.%s: %s -> %s\n", log_id(module), log_id(cell), log_signal(rhs), log_signal(lhs)); } |