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| author | whitequark <whitequark@whitequark.org> | 2019-11-12 00:15:43 +0000 |
|---|---|---|
| committer | whitequark <whitequark@whitequark.org> | 2019-11-12 00:15:43 +0000 |
| commit | c68722818a09ce541c380178ff17e548db9c897d (patch) | |
| tree | a1c1731e4dc90043e22cbcd342bdd630e2fbeae3 /passes/techmap/flowmap.cc | |
| parent | eef32195bd1afb4f029bf3039377e65f0beabac2 (diff) | |
| download | yosys-c68722818a09ce541c380178ff17e548db9c897d.tar.gz yosys-c68722818a09ce541c380178ff17e548db9c897d.tar.bz2 yosys-c68722818a09ce541c380178ff17e548db9c897d.zip | |
flowmap: when doing mincut, ensure source is always in X, not X̅.
Fixes #1475.
Diffstat (limited to 'passes/techmap/flowmap.cc')
| -rw-r--r-- | passes/techmap/flowmap.cc | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/passes/techmap/flowmap.cc b/passes/techmap/flowmap.cc index 96eee45db..a2ad87f7d 100644 --- a/passes/techmap/flowmap.cc +++ b/passes/techmap/flowmap.cc @@ -394,7 +394,7 @@ struct FlowGraph pair<pool<RTLIL::SigBit>, pool<RTLIL::SigBit>> edge_cut() { - pool<RTLIL::SigBit> x, xi; + pool<RTLIL::SigBit> x = {source}, xi; // X and X̅ in the paper NodePrime source_prime = {source, true}; pool<NodePrime> visited; @@ -437,6 +437,7 @@ struct FlowGraph for (auto collapsed_node : collapsed[sink]) xi.insert(collapsed_node); + log_assert(x[source] && !xi[source]); log_assert(!x[sink] && xi[sink]); return {x, xi}; } |