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author | whitequark <whitequark@whitequark.org> | 2020-08-27 11:28:31 +0000 |
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committer | GitHub <noreply@github.com> | 2020-08-27 11:28:31 +0000 |
commit | 2d10d59d93497d0791a5f2be9386b3df05c838d5 (patch) | |
tree | f5e74282619edf25cfb3d586951e3955286ec655 /passes/techmap/flatten.cc | |
parent | 702f7c0253dcf9410050586a5e56da044e3277a3 (diff) | |
parent | 9f0892159ebb88964839ea2cb5313ef1b87c624d (diff) | |
download | yosys-2d10d59d93497d0791a5f2be9386b3df05c838d5.tar.gz yosys-2d10d59d93497d0791a5f2be9386b3df05c838d5.tar.bz2 yosys-2d10d59d93497d0791a5f2be9386b3df05c838d5.zip |
Merge pull request #2356 from whitequark/flatten-techmap-no-tpl_driven-sigmap
flatten, techmap: don't canonicalize tpl driven bits via sigmap
Diffstat (limited to 'passes/techmap/flatten.cc')
-rw-r--r-- | passes/techmap/flatten.cc | 7 |
1 files changed, 3 insertions, 4 deletions
diff --git a/passes/techmap/flatten.cc b/passes/techmap/flatten.cc index b5f55cffa..08978f446 100644 --- a/passes/techmap/flatten.cc +++ b/passes/techmap/flatten.cc @@ -152,15 +152,14 @@ struct FlattenWorker // Attach port connections of the flattened cell - SigMap tpl_sigmap(tpl); pool<SigBit> tpl_driven; for (auto tpl_cell : tpl->cells()) for (auto &tpl_conn : tpl_cell->connections()) if (tpl_cell->output(tpl_conn.first)) - for (auto bit : tpl_sigmap(tpl_conn.second)) + for (auto bit : tpl_conn.second) tpl_driven.insert(bit); for (auto &tpl_conn : tpl->connections()) - for (auto bit : tpl_sigmap(tpl_conn.first)) + for (auto bit : tpl_conn.first) tpl_driven.insert(bit); SigMap sigmap(module); @@ -190,7 +189,7 @@ struct FlattenWorker } else { SigSpec sig_tpl = tpl_wire, sig_mod = port_it.second; for (int i = 0; i < GetSize(sig_tpl) && i < GetSize(sig_mod); i++) { - if (tpl_driven.count(tpl_sigmap(sig_tpl[i]))) { + if (tpl_driven.count(sig_tpl[i])) { new_conn.first.append(sig_mod[i]); new_conn.second.append(sig_tpl[i]); } else { |