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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-15 10:05:08 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-15 10:05:08 -0700 |
| commit | 9f98241010481588d643c6d4e24d7b9af2b37c2f (patch) | |
| tree | 234a3d4424286615e8afa2ebba8d693ba2773489 /passes/techmap/extract_reduce.cc | |
| parent | 4cfefae21e872bb5a4dc13473316352da2b7a916 (diff) | |
| download | yosys-9f98241010481588d643c6d4e24d7b9af2b37c2f.tar.gz yosys-9f98241010481588d643c6d4e24d7b9af2b37c2f.tar.bz2 yosys-9f98241010481588d643c6d4e24d7b9af2b37c2f.zip | |
Transform "$.*" to ID("$.*") in passes/techmap
Diffstat (limited to 'passes/techmap/extract_reduce.cc')
| -rw-r--r-- | passes/techmap/extract_reduce.cc | 18 |
1 files changed, 9 insertions, 9 deletions
diff --git a/passes/techmap/extract_reduce.cc b/passes/techmap/extract_reduce.cc index a77bbc0b7..a126bff9a 100644 --- a/passes/techmap/extract_reduce.cc +++ b/passes/techmap/extract_reduce.cc @@ -58,9 +58,9 @@ struct ExtractReducePass : public Pass inline bool IsRightType(Cell* cell, GateType gt) { - return (cell->type == "$_AND_" && gt == GateType::And) || - (cell->type == "$_OR_" && gt == GateType::Or) || - (cell->type == "$_XOR_" && gt == GateType::Xor); + return (cell->type == ID($_AND_) && gt == GateType::And) || + (cell->type == ID($_OR_) && gt == GateType::Or) || + (cell->type == ID($_XOR_) && gt == GateType::Xor); } void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE @@ -124,11 +124,11 @@ struct ExtractReducePass : public Pass GateType gt; - if (cell->type == "$_AND_") + if (cell->type == ID($_AND_)) gt = GateType::And; - else if (cell->type == "$_OR_") + else if (cell->type == ID($_OR_)) gt = GateType::Or; - else if (cell->type == "$_XOR_") + else if (cell->type == ID($_XOR_)) gt = GateType::Xor; else continue; @@ -291,9 +291,9 @@ struct ExtractReducePass : public Pass SigBit output = sigmap(head_cell->getPort("\\Y")[0]); auto new_reduce_cell = module->addCell(NEW_ID, - gt == GateType::And ? "$reduce_and" : - gt == GateType::Or ? "$reduce_or" : - gt == GateType::Xor ? "$reduce_xor" : ""); + gt == GateType::And ? ID($reduce_and) : + gt == GateType::Or ? ID($reduce_or) : + gt == GateType::Xor ? ID($reduce_xor) : ""); new_reduce_cell->setParam("\\A_SIGNED", 0); new_reduce_cell->setParam("\\A_WIDTH", input.size()); new_reduce_cell->setParam("\\Y_WIDTH", 1); |