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authorSahand Kashani <sahand.kashani@gmail.com>2020-04-08 23:50:37 +0200
committerSahand Kashani <sahand.kashani@gmail.com>2020-04-08 23:50:37 +0200
commit9edf8869c18951ec2b75f074065f073da3253244 (patch)
tree09fba95ba6d3f93ecab828c84b9ff3f74160d7b9 /passes/techmap/extract_reduce.cc
parent820e3d1dad4f484f9646588f79b73b21b495e3d8 (diff)
parent5f649fc19d5cef76a634572ad0a493f1d2fd6306 (diff)
downloadyosys-9edf8869c18951ec2b75f074065f073da3253244.tar.gz
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Merge branch 'master' of github.com:YosysHQ/yosys into firrtl_backend_fileinfo
Diffstat (limited to 'passes/techmap/extract_reduce.cc')
-rw-r--r--passes/techmap/extract_reduce.cc8
1 files changed, 4 insertions, 4 deletions
diff --git a/passes/techmap/extract_reduce.cc b/passes/techmap/extract_reduce.cc
index 11cfddcd9..2d63e413f 100644
--- a/passes/techmap/extract_reduce.cc
+++ b/passes/techmap/extract_reduce.cc
@@ -286,7 +286,7 @@ struct ExtractReducePass : public Pass
SigSpec input;
for (auto b : input_pool)
if (input_pool_intermed.count(b) == 0)
- input.append_bit(b);
+ input.append(b);
SigBit output = sigmap(head_cell->getPort(ID::Y)[0]);
@@ -294,9 +294,9 @@ struct ExtractReducePass : public Pass
gt == GateType::And ? ID($reduce_and) :
gt == GateType::Or ? ID($reduce_or) :
gt == GateType::Xor ? ID($reduce_xor) : "");
- new_reduce_cell->setParam(ID(A_SIGNED), 0);
- new_reduce_cell->setParam(ID(A_WIDTH), input.size());
- new_reduce_cell->setParam(ID(Y_WIDTH), 1);
+ new_reduce_cell->setParam(ID::A_SIGNED, 0);
+ new_reduce_cell->setParam(ID::A_WIDTH, input.size());
+ new_reduce_cell->setParam(ID::Y_WIDTH, 1);
new_reduce_cell->setPort(ID::A, input);
new_reduce_cell->setPort(ID::Y, output);