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author | Jim Lawson <ucbjrl@berkeley.edu> | 2019-08-07 10:14:45 -0700 |
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committer | Jim Lawson <ucbjrl@berkeley.edu> | 2019-08-07 10:14:45 -0700 |
commit | 5e8a98c8fd5f31b514748676804dd1237bce4225 (patch) | |
tree | ead2b0029b55e078abc1023c434b87b4684ba498 /passes/techmap/extract_fa.cc | |
parent | 7e298084e458c3fcccece565df305271db51aec8 (diff) | |
parent | 5545cd3c108ef240ccf6278b2734412acf81cd2a (diff) | |
download | yosys-5e8a98c8fd5f31b514748676804dd1237bce4225.tar.gz yosys-5e8a98c8fd5f31b514748676804dd1237bce4225.tar.bz2 yosys-5e8a98c8fd5f31b514748676804dd1237bce4225.zip |
Merge branch 'master' into firrtl_err_on_unsupported_cell
# Conflicts:
# backends/firrtl/firrtl.cc
Diffstat (limited to 'passes/techmap/extract_fa.cc')
-rw-r--r-- | passes/techmap/extract_fa.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/techmap/extract_fa.cc b/passes/techmap/extract_fa.cc index 591bc43dd..b541ceb6b 100644 --- a/passes/techmap/extract_fa.cc +++ b/passes/techmap/extract_fa.cc @@ -86,7 +86,7 @@ struct ExtractFaWorker for (auto cell : module->selected_cells()) { if (cell->type.in( "$_BUF_", "$_NOT_", "$_AND_", "$_NAND_", "$_OR_", "$_NOR_", - "$_XOR_", "$_XNOR_", "$_ANDNOT_", "$_ORNOT_", "$_MUX_", + "$_XOR_", "$_XNOR_", "$_ANDNOT_", "$_ORNOT_", "$_MUX_", "$_NMUX_", "$_AOI3_", "$_OAI3_", "$_AOI4_", "$_OAI4_")) { SigBit y = sigmap(SigBit(cell->getPort("\\Y"))); |