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author | whitequark <whitequark@whitequark.org> | 2020-06-19 06:15:33 +0000 |
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committer | GitHub <noreply@github.com> | 2020-06-19 06:15:33 +0000 |
commit | ede4b10da8fdbdcff900b93c6c723516901483ff (patch) | |
tree | d949c995f56d6c07dfe7d18ca46547a3296079b6 /passes/techmap/extract.cc | |
parent | bcbd44c673e07c44da735ef1d7f6eb2b6c328f98 (diff) | |
parent | 60478a8e3a7b929ea7e4f4cd1b538b41ca1f34bb (diff) | |
download | yosys-ede4b10da8fdbdcff900b93c6c723516901483ff.tar.gz yosys-ede4b10da8fdbdcff900b93c6c723516901483ff.tar.bz2 yosys-ede4b10da8fdbdcff900b93c6c723516901483ff.zip |
Merge pull request #2173 from whitequark/use-cxx11-final-override
Use C++11 final/override/[[noreturn]]
Diffstat (limited to 'passes/techmap/extract.cc')
-rw-r--r-- | passes/techmap/extract.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/passes/techmap/extract.cc b/passes/techmap/extract.cc index f29044790..7278cb680 100644 --- a/passes/techmap/extract.cc +++ b/passes/techmap/extract.cc @@ -345,7 +345,7 @@ bool compareSortNeedleList(RTLIL::Module *left, RTLIL::Module *right) struct ExtractPass : public Pass { ExtractPass() : Pass("extract", "find subcircuits and replace them with cells") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -433,7 +433,7 @@ struct ExtractPass : public Pass { log("See 'help techmap' for a pass that does the opposite thing.\n"); log("\n"); } - void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector<std::string> args, RTLIL::Design *design) override { log_header(design, "Executing EXTRACT pass (map subcircuits to cells).\n"); log_push(); |