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| author | Clifford Wolf <clifford@clifford.at> | 2018-08-15 14:05:38 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2018-08-15 14:05:38 +0200 |
| commit | 67b10262975340e0b53f8d1072ac2e1c1f087fb1 (patch) | |
| tree | c10a6e56f6f5b61ce3fbff7c165207cc40d704c8 /passes/techmap/extract.cc | |
| parent | d8e40c75eb96e7f3c995b2acd018b5cba6005cdd (diff) | |
| parent | 3aa4484a3cd9a2e82fddd499cde575eaf8c565cc (diff) | |
| download | yosys-67b10262975340e0b53f8d1072ac2e1c1f087fb1.tar.gz yosys-67b10262975340e0b53f8d1072ac2e1c1f087fb1.tar.bz2 yosys-67b10262975340e0b53f8d1072ac2e1c1f087fb1.zip | |
Merge pull request #591 from hzeller/virtual-override
Consistent use of 'override' for virtual methods in derived classes.
Diffstat (limited to 'passes/techmap/extract.cc')
| -rw-r--r-- | passes/techmap/extract.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/passes/techmap/extract.cc b/passes/techmap/extract.cc index 71e29c60b..fff90f13c 100644 --- a/passes/techmap/extract.cc +++ b/passes/techmap/extract.cc @@ -352,7 +352,7 @@ bool compareSortNeedleList(RTLIL::Module *left, RTLIL::Module *right) struct ExtractPass : public Pass { ExtractPass() : Pass("extract", "find subcircuits and replace them with cells") { } - virtual void help() + void help() YS_OVERRIDE { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -440,7 +440,7 @@ struct ExtractPass : public Pass { log("See 'help techmap' for a pass that does the opposite thing.\n"); log("\n"); } - virtual void execute(std::vector<std::string> args, RTLIL::Design *design) + void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE { log_header(design, "Executing EXTRACT pass (map subcircuits to cells).\n"); log_push(); |