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author | Udi Finkelstein <github@udifink.com> | 2018-09-18 01:27:01 +0300 |
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committer | Udi Finkelstein <github@udifink.com> | 2018-09-18 01:27:01 +0300 |
commit | c693f595c53e2e40840ff40b5b5ba06767582d23 (patch) | |
tree | de5e3f353f3222abca7186996e88cd9d635a964b /passes/techmap/dffsr2dff.cc | |
parent | f6fe73b31f6e6d8966ad4ddae860b4d79133cce2 (diff) | |
parent | 592a82c0ad8beb6de023aa2a131aab6472f949e8 (diff) | |
download | yosys-c693f595c53e2e40840ff40b5b5ba06767582d23.tar.gz yosys-c693f595c53e2e40840ff40b5b5ba06767582d23.tar.bz2 yosys-c693f595c53e2e40840ff40b5b5ba06767582d23.zip |
Merge branch 'master' into pr_reg_wire_error
Diffstat (limited to 'passes/techmap/dffsr2dff.cc')
-rw-r--r-- | passes/techmap/dffsr2dff.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/passes/techmap/dffsr2dff.cc b/passes/techmap/dffsr2dff.cc index 0d4d53627..086a1d2fa 100644 --- a/passes/techmap/dffsr2dff.cc +++ b/passes/techmap/dffsr2dff.cc @@ -176,7 +176,7 @@ void adff_worker(SigMap &sigmap, Module *module, Cell *cell) struct Dffsr2dffPass : public Pass { Dffsr2dffPass() : Pass("dffsr2dff", "convert DFFSR cells to simpler FF cell types") { } - virtual void help() + void help() YS_OVERRIDE { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -186,7 +186,7 @@ struct Dffsr2dffPass : public Pass { log("$_DFF_???_) to simpler FF cell types when any of the set/reset inputs is unused.\n"); log("\n"); } - virtual void execute(std::vector<std::string> args, RTLIL::Design *design) + void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE { log_header(design, "Executing DFFSR2DFF pass (mapping DFFSR cells to simpler FFs).\n"); |