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author | Eddie Hung <eddie@fpgeh.com> | 2019-08-15 10:19:29 -0700 |
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committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-15 10:19:29 -0700 |
commit | 78ba8b85749abacdf9a6953fd2e6f430b6041a94 (patch) | |
tree | 06641220842902317fd89a76e5f1726b6a6abe8d /passes/techmap/dfflibmap.cc | |
parent | 9f98241010481588d643c6d4e24d7b9af2b37c2f (diff) | |
download | yosys-78ba8b85749abacdf9a6953fd2e6f430b6041a94.tar.gz yosys-78ba8b85749abacdf9a6953fd2e6f430b6041a94.tar.bz2 yosys-78ba8b85749abacdf9a6953fd2e6f430b6041a94.zip |
Transform all "\\*" identifiers into ID()
Diffstat (limited to 'passes/techmap/dfflibmap.cc')
-rw-r--r-- | passes/techmap/dfflibmap.cc | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/passes/techmap/dfflibmap.cc b/passes/techmap/dfflibmap.cc index abe73c258..b10c7042d 100644 --- a/passes/techmap/dfflibmap.cc +++ b/passes/techmap/dfflibmap.cc @@ -485,7 +485,7 @@ static void dfflibmap(RTLIL::Design *design, RTLIL::Module *module, bool prepare if (design->selected(module, it.second) && cell_mappings.count(it.second->type) > 0) cell_list.push_back(it.second); if (it.second->type == ID($_NOT_)) - notmap[sigmap(it.second->getPort("\\A"))].insert(it.second); + notmap[sigmap(it.second->getPort(ID(\\A)))].insert(it.second); } std::map<std::string, int> stats; @@ -519,8 +519,8 @@ static void dfflibmap(RTLIL::Design *design, RTLIL::Module *module, bool prepare sig = module->addWire(NEW_ID, GetSize(old_sig)); if (has_q && has_qn) { for (auto &it : notmap[sigmap(old_sig)]) { - module->connect(it->getPort("\\Y"), sig); - it->setPort("\\Y", module->addWire(NEW_ID, GetSize(old_sig))); + module->connect(it->getPort(ID(\\Y)), sig); + it->setPort(ID(\\Y), module->addWire(NEW_ID, GetSize(old_sig))); } } else { module->addNotGate(NEW_ID, sig, old_sig); |