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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-23 10:00:50 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-23 10:00:50 -0700 |
| commit | 6872805a3eb738a0a5921b232022abfd507cebb8 (patch) | |
| tree | b871344e8f96cd30c5a6bc3f275476e30f792de0 /passes/techmap/dfflibmap.cc | |
| parent | 6b51c154c6812f58676402ebbbdbb18d053ca4be (diff) | |
| parent | bb2d5bc4f85ac95104fbd2591ad92ebf0c22e11d (diff) | |
| download | yosys-6872805a3eb738a0a5921b232022abfd507cebb8.tar.gz yosys-6872805a3eb738a0a5921b232022abfd507cebb8.tar.bz2 yosys-6872805a3eb738a0a5921b232022abfd507cebb8.zip | |
Merge remote-tracking branch 'origin/master' into mwk/xilinx_bufgmap
Diffstat (limited to 'passes/techmap/dfflibmap.cc')
| -rw-r--r-- | passes/techmap/dfflibmap.cc | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/passes/techmap/dfflibmap.cc b/passes/techmap/dfflibmap.cc index 7478e020d..b15109cd3 100644 --- a/passes/techmap/dfflibmap.cc +++ b/passes/techmap/dfflibmap.cc @@ -485,7 +485,7 @@ static void dfflibmap(RTLIL::Design *design, RTLIL::Module *module, bool prepare if (design->selected(module, it.second) && cell_mappings.count(it.second->type) > 0) cell_list.push_back(it.second); if (it.second->type == ID($_NOT_)) - notmap[sigmap(it.second->getPort(ID(A)))].insert(it.second); + notmap[sigmap(it.second->getPort(ID::A))].insert(it.second); } std::map<std::string, int> stats; @@ -519,8 +519,8 @@ static void dfflibmap(RTLIL::Design *design, RTLIL::Module *module, bool prepare sig = module->addWire(NEW_ID, GetSize(old_sig)); if (has_q && has_qn) { for (auto &it : notmap[sigmap(old_sig)]) { - module->connect(it->getPort(ID(Y)), sig); - it->setPort(ID(Y), module->addWire(NEW_ID, GetSize(old_sig))); + module->connect(it->getPort(ID::Y), sig); + it->setPort(ID::Y, module->addWire(NEW_ID, GetSize(old_sig))); } } else { module->addNotGate(NEW_ID, sig, old_sig); |