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| author | Jim Lawson <ucbjrl@berkeley.edu> | 2018-08-22 08:42:34 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2018-08-22 08:42:34 -0700 |
| commit | 2c0601eb6f2c5ed0d376ed880efda48a2aeeb9ef (patch) | |
| tree | 02b9412c9249cce3714972c8385d66f8093bfc17 /passes/techmap/dfflibmap.cc | |
| parent | 8b92ddb9d2635c30636b17ff3d24bc09a44b8551 (diff) | |
| parent | 408077769ff022f78f10ec1ffb60926361f8dc9f (diff) | |
| download | yosys-2c0601eb6f2c5ed0d376ed880efda48a2aeeb9ef.tar.gz yosys-2c0601eb6f2c5ed0d376ed880efda48a2aeeb9ef.tar.bz2 yosys-2c0601eb6f2c5ed0d376ed880efda48a2aeeb9ef.zip | |
Merge pull request #1 from YosysHQ/master
merge with YosysHQ master
Diffstat (limited to 'passes/techmap/dfflibmap.cc')
| -rw-r--r-- | passes/techmap/dfflibmap.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/passes/techmap/dfflibmap.cc b/passes/techmap/dfflibmap.cc index 5ccb770c4..416ed2bd5 100644 --- a/passes/techmap/dfflibmap.cc +++ b/passes/techmap/dfflibmap.cc @@ -537,7 +537,7 @@ static void dfflibmap(RTLIL::Design *design, RTLIL::Module *module, bool prepare struct DfflibmapPass : public Pass { DfflibmapPass() : Pass("dfflibmap", "technology mapping of flip-flops") { } - virtual void help() + void help() YS_OVERRIDE { log("\n"); log(" dfflibmap [-prepare] -liberty <file> [selection]\n"); @@ -553,7 +553,7 @@ struct DfflibmapPass : public Pass { log("liberty file.\n"); log("\n"); } - virtual void execute(std::vector<std::string> args, RTLIL::Design *design) + void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE { log_header(design, "Executing DFFLIBMAP pass (mapping DFF cells to sequential cells from liberty file).\n"); |