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authorClifford Wolf <clifford@clifford.at>2019-05-06 15:41:13 +0200
committerClifford Wolf <clifford@clifford.at>2019-05-06 15:41:13 +0200
commitd187be39d608966f53d6c2ba4d45de94a584d476 (patch)
tree30b9820eddba4341c7270d5b255758967ed7eaf0 /passes/techmap/dffinit.cc
parent5c2c0b4bb2ade51396da3acbcce0d5916fb1c7d6 (diff)
parent20268d12a51e157effc209de5613f0ac8308a61f (diff)
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Merge branch 'master' of github.com:YosysHQ/yosys into clifford/fix968
Diffstat (limited to 'passes/techmap/dffinit.cc')
-rw-r--r--passes/techmap/dffinit.cc3
1 files changed, 2 insertions, 1 deletions
diff --git a/passes/techmap/dffinit.cc b/passes/techmap/dffinit.cc
index 48390488e..0ad33dc0e 100644
--- a/passes/techmap/dffinit.cc
+++ b/passes/techmap/dffinit.cc
@@ -102,7 +102,8 @@ struct DffinitPass : public Pass {
if (wire->attributes.count("\\init")) {
Const value = wire->attributes.at("\\init");
for (int i = 0; i < min(GetSize(value), GetSize(wire)); i++)
- init_bits[sigmap(SigBit(wire, i))] = value[i];
+ if (value[i] != State::Sx)
+ init_bits[sigmap(SigBit(wire, i))] = value[i];
}
if (wire->port_output)
for (auto bit : sigmap(wire))