aboutsummaryrefslogtreecommitdiffstats
path: root/passes/techmap/attrmap.cc
diff options
context:
space:
mode:
authorEddie Hung <eddie@fpgeh.com>2019-07-15 08:23:01 -0700
committerEddie Hung <eddie@fpgeh.com>2019-07-15 08:23:01 -0700
commit7129a03083b21c1ed1610126ae28828c56f42369 (patch)
tree03de1a2fe3dceb28b5e840fb5b1da9cbff8dc029 /passes/techmap/attrmap.cc
parent44fd459c799e393d13d664102cf381264c80649f (diff)
parenta97d30d2f88d2f7a41abf8b913bbc017b60d8c7d (diff)
downloadyosys-7129a03083b21c1ed1610126ae28828c56f42369.tar.gz
yosys-7129a03083b21c1ed1610126ae28828c56f42369.tar.bz2
yosys-7129a03083b21c1ed1610126ae28828c56f42369.zip
Merge branch 'master' into eddie/fix1178
Diffstat (limited to 'passes/techmap/attrmap.cc')
-rw-r--r--passes/techmap/attrmap.cc19
1 files changed, 19 insertions, 0 deletions
diff --git a/passes/techmap/attrmap.cc b/passes/techmap/attrmap.cc
index aa48e1125..a38638e0b 100644
--- a/passes/techmap/attrmap.cc
+++ b/passes/techmap/attrmap.cc
@@ -263,6 +263,25 @@ struct AttrmapPass : public Pass {
for (auto cell : module->selected_cells())
attrmap_apply(stringf("%s.%s", log_id(module), log_id(cell)), actions, cell->attributes);
+
+ for (auto proc : module->processes)
+ {
+ if (!design->selected(module, proc.second))
+ continue;
+ attrmap_apply(stringf("%s.%s", log_id(module), log_id(proc.first)), actions, proc.second->attributes);
+
+ std::vector<RTLIL::CaseRule*> all_cases = {&proc.second->root_case};
+ while (!all_cases.empty()) {
+ RTLIL::CaseRule *cs = all_cases.back();
+ all_cases.pop_back();
+ attrmap_apply(stringf("%s.%s (case)", log_id(module), log_id(proc.first)), actions, cs->attributes);
+
+ for (auto &sw : cs->switches) {
+ attrmap_apply(stringf("%s.%s (switch)", log_id(module), log_id(proc.first)), actions, sw->attributes);
+ all_cases.insert(all_cases.end(), sw->cases.begin(), sw->cases.end());
+ }
+ }
+ }
}
}
}