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| author | Eddie Hung <eddie@fpgeh.com> | 2019-06-12 16:04:33 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-12 16:04:33 -0700 |
| commit | b3faf0246d46f31027ce2aade410e4325822b121 (patch) | |
| tree | 9d7bbcb1495edfb47c6e7c935b83a4b0fdce86bd /passes/techmap/abc9.cc | |
| parent | 8374eb1cb4dcb99b2125543a3d5f9f6adbdd6b7d (diff) | |
| download | yosys-b3faf0246d46f31027ce2aade410e4325822b121.tar.gz yosys-b3faf0246d46f31027ce2aade410e4325822b121.tar.bz2 yosys-b3faf0246d46f31027ce2aade410e4325822b121.zip | |
Be more precise when connecting during ABC9 re-integration
Diffstat (limited to 'passes/techmap/abc9.cc')
| -rw-r--r-- | passes/techmap/abc9.cc | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc index 21d207d33..c3145dbe5 100644 --- a/passes/techmap/abc9.cc +++ b/passes/techmap/abc9.cc @@ -569,7 +569,9 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri RTLIL::SigBit y_bit = c->getPort("\\Y").as_bit(); if (!a_bit.wire) { c->setPort("\\Y", module->addWire(NEW_ID)); - module->connect(module->wires_[remap_name(y_bit.wire->name)], RTLIL::S1); + RTLIL::Wire *wire = module->wire(remap_name(y_bit.wire->name)); + log_assert(wire); + module->connect(RTLIL::SigBit(wire, y_bit.offset), RTLIL::S1); } else if (!lut_costs.empty() || !lut_file.empty()) { RTLIL::Cell* driving_lut = nullptr; |